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參數(shù)資料
| 型號： | DSM2180F3V90T6 |
| 廠商： | 意法半導體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號處理器系統(tǒng)內(nèi)存）模擬器件公司的ADSP - 218X系列（5V電源） |
| 文件頁數(shù)： | 26/63頁 |
| 文件大?。?/td> | 809K |
| 代理商： | DSM2180F3V90T6 |
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DSM2180F3
26/63
The DPLD performs address decoding, and gen-
erates select signals for internal and external com-
ponents, such as memory, registers, and I/O ports.
The DPLD can generates External Chip Select
(ECS0-ECS2) signals on Port D.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 16 Input Macrocells
(IMC), and the AND Array.
The AND Array is used to form product terms.
These product terms are configured from the logic
definition entered in PSDsoft Express. An Input
Bus consisting of 64 signals is connected to the
PLDs. Input signals are shown in Table 9.
Turbo Bit.
The PLDs in the device can minimize
power consumption by switching off when inputs
remain unchanged for an extended time of about
70 ns. Resetting the Turbo bit to 0 (Bit 3 of the
PMMR0 register) automatically places the PLDs
into standby if no inputs are changing. Turning the
Turbo mode off increases propagation delays
while reducing power consumption. Additionally,
five bits are available in the PMMR registers in
csiopto block DSP control signals from entering
the PLDs. This reduces power consumption and
can be used only when these DSP control signals
are not used in PLD logic equations. Each of the
two PLDs has unique characteristics suited for its
applications. They are described in the following
sections.
Figure 13. PLD Diagram
P
8
Input Macrocell and Input Ports
Direct Macrocell Input to MCU Data Bus
CSIOP Select
DECODE PLD
(DPLD)
PAGE
REGISTER
External Chip Selects to PORT D
JTAG Select
CPLD
PT
ALLOC.
Macrocell
Alloc.
MCELLAB
to PORT B
MCELLBC
to PORT B or C
Direct Macrocell Access from MCU Data Bus
16 Input Macrocell
(PORT B,C)
16 Output
Macrocell
I
Flash Memory Selects
3
PORT D Inputs
Data
Bus
8
8
8
1
3
1
64
16
64
16
Output Macrocell Feedback
AI04900B
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| DSM2190F4V | 16-bit fixed point DSP with Flash |
| DSM2190F4V-15K6 | 16-bit fixed point DSP with Flash |
| DSM2190F4V-15T6 | 16-bit fixed point DSP with Flash |
| DSM3MA | GENERAL-USE RECTIFIER DIODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSM2180F3V-90T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) for analog devices ADSP-218X family (5 V supply) |
| DSM2190F4 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply) |
| DSM2190F4V | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply) |
| DSM2190F4V-15K6 | 功能描述:SPLD - 簡單可編程邏輯器件 3.3V 16M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| DSM2190F4V-15T6 | 功能描述:SPLD - 簡單可編程邏輯器件 3.3V 16M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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