參數(shù)資料
型號(hào): DSP102JP
英文描述: DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
中文描述: DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 19/22頁(yè)
文件大?。?/td> 252K
代理商: DSP102JP
DSP101/102
19
SERIAL PORT
Port Global Control Register
FSX/DX/CLKX Port Control Register
FSR/DR/CLKR Port Control Register
Receive/Transmit Timer Control Register
0x0EBC040
0x00000111
0x00000111
0x0000000F
TIMER
Timer Global Control Register
Timer Period Register
0x000002C1
0x000000B5
NOTE: Assumes TMS320C31 has 32MHz Master Clock.
USING TMS320C31 TO GENERATE
ALL CONTROL SIGNALS
Figure 17 shows a circuit for using the TMS320C31 with a
DSP102 and a Burr-Brown DSP202 D/A to provide a two
channel analog I/O system. The flexibility of the TMS320C31
allows it to generate the data transfer clock (XCLK) and the
Convert Command, minimizing additional circuitry and syn-
chronizing the timing signals to the processor’s master
clock. In this circuit, the DSP102 and DSP202 are used in
their Cascade modes, transmitting and receiving two chan-
nels of data in a single 32-bit word. (See the Cascade Mode
section above.)
Table II shows how to set up the circuit in Figure 17 for a
44.1kHz conversion rate for both channels of the DSP102
A/D and both channels of the DSP202 D/A. Both inputs and
outputs will be simultaneously converted.
XCLK
SYNC
SOUT
SSF
CONV
VIN
DSP101
TTL Bit
Clock
Conversion Rate
Generator
XCLK
FSX
TXD
±2.75V Analog Input
16
15
20
12
21
+5V
NOTES: (1) TMS320C25 FSR external, 16-bit data.
2
TMS320C25
FIGURE 16. Using DSP101 with TMS320C25.
FIGURE 17. Two Channel Analog I/O Using TMS320C31.
1M
XCLK
SINA
SINB
SYNC
SSF
SWL
CASC
CONV
±3V Analog Output
Channel A
VOUTA
DSP202
XCLK
SYNC
CASC
DSP102
±2.75V Analog Input
Channel A
DR0
FSR0
DX0
FSX0
+5V
VINA
TMS3200C31
CONV
VINB
OSC2
OSC1
TCLK0
+5V
±3V Analog Output
Channel B
VOUTB
+5V
+5V
+5V
10pF
10pF
12.288MHz
±2.75V Analog Input
Channel B
SOUTA
SOUTB
SSF
NC
CLKX0
TABLE II. TMS320C31 Register Settings for 44.1kHz Con-
version Rate in Figure 17.
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