參數(shù)資料
型號: DSP102JP
英文描述: DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
中文描述: DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 21/22頁
文件大小: 252K
代理商: DSP102JP
DSP101/102
21
USING DSP101 AND DSP102 WITH ADI DSP ICS
When using the DSP101 or DSP102 with the fixed-point
ADSP21xx series, the processors need to be programmed to
receive data MSB-first.
Figure 22 shows how to use the DSP102 with an ADSP2101
to provide a two-channel simultaneous sampling system.
Figure 23 shows the connections required to generate an
analog input channel using an ADSP2105 with the DSP101.
The same basic circuit can be used to connect a DSP101 to
the ADSP2101.
Figure 11 indicates how to build a complete analog I/O
system using either the ADSP2101 or the ADSP2105 with a
DSP101 and a Burr-Brown DSP201 D/A.
The two serial ports on the ADSP2101 can also be used with
the DSP102 and the Burr-Brown DSP202 D/A to make two
complete analog I/O channels, as indicated in footnote 2 of
Figure 14.
TTL Bit
Clock
16
20
15
12
ICK
DATA IN
ILD
±2.75V Analog Input
2
VIN
DSP16
Conversion Rate
Generator
DSP101
XCLK
SOUT
SYNC
SSF
NOTE: DSP16 programmed for MSB bit first, 16-bit data.
21
CONV
FIGURE 20. Using DSP101 with DSP16.
FIGURE 21. Using DSP102 with DSP32C in Cascade Mode.
XCLK
SYNC
SOUTA
SOUTB
CASC
SSF
CONV
VINA
VINB
DSP102
TTL Bit
Clock
Conversion Rate
Generator
ICK
ILD
DATA IN
±2.75V Analog Input
Channel A
±2.75V Analog Input
Channel B
16
15
20
17
22
12
21
NOTES: (1) DSP32C programmed 32-bit data MSB bit first. (2) Data format is Channel A, 16 bits, MSB first, then Channel B.
2
DSP32C
25
NC
+5V
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