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參數(shù)資料
| 型號： | DSP102JP |
| 英文描述： | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 252K |
| 代理商： | DSP102JP |
DSP101/102
6
DSP102 PIN ASSIGNMENTS
PIN #
NAME
DESCRIPTION
1
VPOTA
Channel A Trim Reference Out. 10
μ
F Tantalum to
AGND. Voltage on this pin is approximately 2.75V.
Channel A Analog In.
Channel A MSB Adjust In.
Channel A VOS Adjust In.
–5V Analog Power.
+5V Analog Power.
Digital Ground.
Digital Ground.
+5V Digital Power.
Conversion Clock In.
Conversion Clock Out. Can drive multiple DSP101/
DSP102s to synchronize conversion.
Select Synch Format In. If HIGH, SYNC will be
active High. If LOW, SYNC will be active Low. See
timing diagram (Figure 1).
Oscillator Point 1 Input / External Clock In. If using
external clock, drive with 74HC logic levels.
Connect to DGND if not used.
Oscillator Point 2 Output. Provides drive for crystal
oscillator. Make no electrical connection if using
external clock.
Data Synchronization Out. Active High when SSF
is HIGH; active Low when SSF is LOW.
Data Transfer Clock In.
Channel B Serial Data Out. MSB first, Binary
Two’s Complement format.
Channel A User Tag In. Data clocked into this pin
is appended to the conversion results of SOUTA.
See timing diagram (Figure 1).
Channel B User Tag In. Data clocked into this pin
is appended to the conversion results of SOUTB.
See timing diagram (Figure 1).
Channel A Serial Data Out. MSB first, Binary
Two’s Complement format. If CASC is HIGH, 32
bits of data output, with first 16 bits being Channel
A data.
Convert Command In. Falling edge puts converter
into hold state, initiates conversion, and transmits
previous conversion results to DSP IC with
appropriate SYNC pulse.
Select Cascade Mode In. If HIGH, DSP102
transmits a 32-bit word on SOUTA, with the first 16
bits being data on Channel A. If LOW, DSP102
transmits data for both channels simultaneously.
Channel B VOS Adjust In.
Channel B MSB Adjust In.
Channel B Analog In.
Channel B Trim Reference Out. 10
μ
F Tantalum to
AGND. Voltage on this pin is approximately 2.75V.
Reference Bypass. 0.1
μ
F Ceramic to AGND.
Voltage on this pin is approximately 3.8V.
Analog Ground.
2
3
4
5
6
7
8
9
VINA
MSBA
VOSA
V
A
–
V
+
DGND
DGND
V
CLKIN
CLKOUT
10
11
12
SSF
13
OSC1
14
OSC2
15
SYNC
16
17
XCLK
SOUTB
18
TAGA
19
TAGB
20
SOUTA
21
CONV
22
CASC
23
24
25
26
VOSB
MSBB
VINB
VPOTB
27
REF
28
AGND
DSP102 PIN CONFIGURATION
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
Top View
DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VPOTA
VINA
MSBA
VOSA
V
A
–
V
A
+
DGND
DGND
V
D
CLKIN
CLKOUT
SSF
OSC1
OSC2
AGND
REF
VPOTB
VINB
MSBB
VOSB
CASC
CONV
SOUTA
TAGB
TAGA
SOUTB
XCLK
SYNC
DSP102
ORDERING INFORMATION
NUMBER
OF
CHANNELS
SIGNAL-TO-
(NOISE + DIST.) RATIO
dB min
MODEL
DSP101JP
DSP101KP
DSP102JP
DSP102KP
1
1
2
2
83
86
83
86
PACKAGE INFORMATION
PACKAGE DRAWING
NUMBER
(1)
MODEL
PACKAGE
DSP101JP
DSP101KP
DSP102JP
DSP102KP
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin Plastic DIP
215
215
215
215
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
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| DSP102JP-1 | 制造商:BB 制造商全稱:BB 功能描述:DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| DSP102KP | 制造商:BB 制造商全稱:BB 功能描述:DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
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