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參數(shù)資料
| 型號： | DSP102JP |
| 英文描述： | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 252K |
| 代理商： | DSP102JP |
DSP101/102
2
SPECIFICATIONS
ELECTRICAL
At T
= 0
°
C to 70
°
C,
±
2.75V input signal, sampling frequency (f
) = 200kHz, V
+ = V
= +5V, V
– = –5V, 16MHz external clock on OSC1, CLKOUT tied to CLKIN,
8MHzdata transfer clock on XCLK, data analysis band-limited to 20kHz, unless otherwise specified.
Sufficient to meet AC Accuracy Specifications
Sufficient to meet AC Accuracy Specifications
±
0.003
±
0.002
14
±
2
±
2
–60
–60
DSP101JP
DSP102JP
DSP101KP
DSP102KP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
RESOLUTION
18
*
Bits
ANALOG INPUT
Voltage Range
Impedance
Capacitance
±
2.75V
1
20
*
*
*
V
k
pF
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Acquisition + Conversion
5
*
μ
s
kHz
200
*
AC ACCURACY
(1)
Signal-to-(Noise + Distortion) Ratio
f
= 1kHz
f
IN
= 1kHz (–60dB)
f
IN
= 25kHz
f
IN
= 1kHz
f
IN
= 1kHz
f
IN
= 1kHz
83
86
32
82
–90
92
88
86
88
*
*
–91
94
89
dB
(2)
dB
dB
dB
dB
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Signal-to-Noise Ratio (SNR)
–86
–89
89
84
92
87
DC ACCURACY
Gain Error
Gain Error Mismatch
Integral Linearity
Differential Linearity
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Bipolar Zero Error
(3)
Bipolar Zero Mismatch
(3)
Power Supply Sensitivity
±
5
±
2
*
*
%
%
DSP102 Channels
±
2.75V Input Range
±
2.75V Input Range
±
0.7V Input Range
±
0.7V Input Range
±
0.7V Input Range
*
*
*
%
%
Bits
mV
mV
dB
dB
DSP102 Channels
–5.25V < V
– < –4.75V
+4.75V < V
A
+, V
D
+ < +5.25V
*
*
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery
30
100
1
5
*
*
*
*
ns
ps, rms
μ
s
μ
s
DIGITAL INPUTS
Logic Levels (Except OSC1)
V
IL
V
OSC1 Clock
Frequency
Data Transfer Clock (XCLK)
Frequency
Duty Cycle
Conversion Clock (CLKIN)
Frequency
Duty Cycle
I
L
=
±
10
μ
A
I
H
=
±
10
μ
A
0
+0.8
+5
*
*
*
*
V
V
+2.4
74HC Compatible
16
MHz
0.1
40
12
60
*
*
*
*
MHz
%
50
0.5
25
5.33
55
*
*
*
*
MHz
%
33
*
DIGITAL OUTPUTS
Format
Coding
Logic Levels (Except OSC2)
V
OL
V
OSC2
Conversion Clock (CLKOUT)
Drive Capability
Serial; MSB first; 16/18-bit and Cascaded 32-bit Mode
Binary Two’s Complement
I
SINK
= 4mA
I
SOURCE
= 4mA
0
+0.4
+5
*
*
*
*
V
V
+2.4
Can only be used to drive crystal oscillator.
±
2mA
*
mA
POWER SUPPLIES
Rated Voltage
V
A
+
V
A
–
V
Power Consumption
Supply Current
I
A
+
I
A
–
I
D
TEMPERATURE RANGE
Specification
Storage
+4.75
–5.25
+4.75
+5
–5
+5
250
+5.25
–4.75
+5.25
425
*
*
*
*
*
*
*
*
*
*
*
V
V
V
XCLK = OSC1 = 12MHz
XCLK = OSC1 = 12MHz
mW
30
–18
5
45
–25
15
*
*
*
*
*
*
mA
mA
mA
0
+70
+125
*
*
*
*
o
C
o
C
–65
NOTES: (1) All dynamic specifications are based on 2048-point FFTs, using four-term Blackman-Harris window. (2) All specifications in dB are referred to a full-
scale input,
±
2.75Vp-p. (3) Adjustable to zero with external potentiometer.
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