參數(shù)資料
型號: DSP56364P
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: 24-Bit Audio Digital Signal Processor
中文描述: 24位音頻數(shù)字信號處理器
文件頁數(shù): 21/148頁
文件大?。?/td> 1204K
代理商: DSP56364P
EXTERNAL CLOCK OPERATION
DSP56364 Technical Data, Rev. 4
Freescale Semiconductor
3-5
3.7
EXTERNAL CLOCK OPERATION
The DSP56364 system clock is an externally supplied square wave voltage source connected to
EXTAL(See
Figure 3-1
).
Figure 3-1 External Clock Timing
Internal clock low period
T
L
With PLL disabled
ET
C
With PLL enabled and MF
4
0.49
×
ET
C
×
PDF
×
DF/MF
0.51
×
ET
C
×
PDF
×
DF/MF
With PLL enabled and MF > 4
0.47
×
ET
C
×
PDF
×
DF/MF
0.53
×
ET
C
×
PDF
×
DF/MF
Internal clock cycle time with PLL enabled
T
C
ET
C
×
PDF
×
DF/MF
Internal clock cycle time with PLL disabled
T
C
2
×
ET
C
Instruction cycle time
I
CYC
T
C
1
DF = Division Factor
Ef = External frequency
ET
C
= External clock cycle
MF = Multiplication Factor
PDF = Predivision Factor
T
C
= internal clock cycle
2
See the
PLL and Clock Generation
section in the
DSP56300 Family Manual
for a detailed discussion of the PLL.
Table 3-4 Internal Clocks (continued)
Characteristics
Symbol
Expression
1, 2
Min
Typ
Max
EXTAL
V
ILC
V
IHC
Midpoint
Note: The midpoint is 0.5 (V
IHC
+ V
ILC
).
ETH
ETL
ETC
3
4
2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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