- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377001 > DSP56F803E (飛思卡爾半導(dǎo)體(中國(guó))有限公司) 16-bit Digital Signal Controllers PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP56F803E |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號(hào)控制器 |
| 文件頁數(shù)： | 12/52頁 |
| 文件大?。?/td> | 414K |
| 代理商： | DSP56F803E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
56F803 Technical Data, Rev. 15
12
Freescale Semiconductor
2.5 Interrupt and Program Control Signals
Table 2-7 Data Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
16
D0–D15
Input/O
utput
Tri-stated
Data Bus
— D0–D15 specify the data for external Program or Data
memory accesses. D0–D15 are tri-stated when the external bus is
inactive. Internal pull-ups may be active.
Table 2-8 Bus Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
PS
Output
Tri-stated
Program Memory Select
—PS is asserted low for external Program memory
access.
1
DS
Output
Tri-stated
Data Memory Select
—DS is asserted low for external Data memory access.
1
WR
Output
Tri-stated
Write Enable
—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the device puts data
on the bus. When WR is deasserted high, the external data is latched inside
the external device. When WR is asserted, it qualifies the A0–A15, PS, and
DS pins. WR can be connected directly to the WE pin of a Static RAM.
1
RD
Output
Tri-stated
Read Enable
—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device data bus. When RD is deasserted high, the external
data is latched inside the controller. When RD is asserted, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a
Static RAM or ROM.
Table 2-9 Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
IRQA
Input
(Schmitt)
Input
External Interrupt Request A
—The IRQA input is a synchronized
external interrupt request indicating an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge- triggered.
1
IRQB
Input
(Schmitt)
Input
External Interrupt Request B
—The IRQB input is an external
interrupt request indicating an external device is requesting service.
It can be programmed to be level-sensitive or
negative-edge-triggered.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56F805E | 16-bit Digital Signal Controllers |
| DSP56F805FV80E | 16-bit Digital Signal Controllers |
| DSP56F805 | 16-bit Hybrid Controller(16位混合控制器) |
| DSP56F807PY80E | 16-bit Digital Signal Controllers |
| DSP56F807VF80E | 16-bit Digital Signal Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F803EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F803 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| DSP56F803EVMUM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F803 Evaluation Module Hardware User＇s Manual |
| DSP56F803PB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F803 16-Bit Hybrid Controller Product Brief |
| DSP56F805 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F805ACIM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Targeting Document for the 56F805 3-Phase AC Induction Motor V/Hz Control |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。