參數資料
型號: DSP56F803E
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數字信號控制器
文件頁數: 32/52頁
文件大?。?/td> 414K
代理商: DSP56F803E
56F803 Technical Data, Rev. 15
32
Freescale Semiconductor
Figure 3-11 External Bus Asynchronous Timing
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1.
T = Clock Period. For 80MHz operation, T = 12.5ns.
Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +85
°
C, C
L
50pF
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
21
ns
Figure 3-12
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
t
RA
275,000T
128T
ns
ns
Figure 3-12
RESET De-assertion to First External Address Output
t
RDA
33T
34T
ns
Figure 3-12
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Data In
Data Out
t
AWR
t
ARDA
t
ARDD
t
RDA
t
RD
t
RDRD
t
RDWR
t
WRWR
t
WR
t
DOS
t
WRD
t
WRRD
t
AD
t
DOH
t
DRD
t
RDD
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