參數(shù)資料
型號: DSP56F805
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數(shù): 14/48頁
文件大小: 967K
代理商: DSP56F805
14
56F805 Technical Data
2.11 CAN Signals
2.12 Analog-to-Digital Converter (ADC) Signals
Table 17. Analog to Digital Converter Signals
1
RXD0
GPIOE1
Input
Input/
Output
Input
Input
Receive Data (RXD0)
— SCI0 receive data input
Port E GPIO
—This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.
After reset, the default state is SCI input.
1
TXD1
GPIOD6
Output
Input/
Output
Input
Input
Transmit Data (TXD1)
—SCI1 transmit data output
Port D GPIO
—This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as an input or output pin.
After reset, the default state is SCI output.
1
RXD1
GPIOD7
Input
Input/
Output
Input
Input
Receive Data (RXD1)
—SCI1 receive data input
Port D GPIO
—This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as an input or output pin.
After reset, the default state is SCI input.
Table 16. CAN Module Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
MSCAN_ RX
Input
(Schmitt)
Input
MSCAN Receive Data
—This is the MSCAN input. This
pin has an internal pull-up resistor.
1
MSCAN_ TX
Output
Output
MSCAN Transmit Data
—MSCAN output. CAN output is
open-drain output and a pull-up resistor is needed.
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
4
ANA0
3
Input
Input
ANA0
3
—Analog inputs to ADC channel 1
4
ANA4
7
Input
Input
ANA4
7
—Analog inputs to ADC channel 2
1
VREF
Input
Input
VREF
—Analog reference voltage for ADC. Must be set to
V
DDA
- 0.3V for optimal performance.
Table 15. Serial Communications Interface (SCI0 and SCI1) Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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