參數(shù)資料
型號: DSP56F805
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數(shù): 47/48頁
文件大?。?/td> 967K
代理商: DSP56F805
Electrical Design Considerations
56F805 Technical Data
47
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V
DD
and V
SS
circuits.
Take special care to minimize noise levels on the V
REF
, V
DDA
and V
SSA
pins.
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at
power up for proper operation. Designs that do not require debugging functionality, such as
consumer products, TRST should be tied low.
TRST must be externally asserted even when the user relies on the internal power on reset for
functional test purposes.
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.
Part 6 Ordering Information
Table 39
lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales
office or authorized distributor to determine availability and to order parts.
Table 39. 56F805 Ordering Information
Part
Supply
Voltage
Package Type
Pin
Count
Frequency
(MHz)
Order Number
56F805
3.0–3.6 V
Low Profile Plastic Quad Flat Pack
(LQFP)
144
80
DSP56F805FV80
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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