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參數(shù)資料
| 型號： | DSP56F805 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 16-bit Hybrid Controller(16位混合控制器) |
| 中文描述： | 16位混合控制器（16位混合控制器） |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 967K |
| 代理商： | DSP56F805 |
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28
56F805 Technical Data
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 30. Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 6
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF
Figure 13. External Bus Asynchronous Timing
Characteristic
Symbol
Min
Max
Unit
See
Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
—
21
ns
Figure 14
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
t
RA
275,000T
128T
—
—
ns
ns
Figure 14
RESET Deassertion to First External Address Output
t
RDA
33T
34T
ns
Figure 14
Edge-sensitive Interrupt Request Width
t
IRW
1.5T
—
ns
Figure 15
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
t
IDM
15T
—
ns
Figure 16
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
16T
—
ns
Figure 16
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
3
t
IRI
13T
—
ns
Figure 17
IRQA Width Assertion to Recover from Stop State
4
t
IW
2T
—
ns
Figure 18
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Data In
Data Out
t
AWR
t
ARDA
t
ARDD
t
RDA
t
RD
t
RDRD
t
RDWR
t
WRWR
t
WR
t
DOS
t
WRD
t
WRRD
t
AD
t
DOH
t
DRD
t
RDD
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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