V
參數(shù)資料
型號(hào)： DSP56F805FV80E
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 16/56頁(yè)
文件大?。?/td> 0K
描述： IC DSP 80MHZ 64KB FLASH 144LQFP
標(biāo)準(zhǔn)包裝： 60
系列： 56F8xx
核心處理器： 56800
芯體尺寸： 16-位
速度： 80MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 71KB（35.5K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2.5K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
包裝： 托盤
DC Electrical Characteristics
56F805 Technical Data, Rev. 16
Freescale Semiconductor
23
Output Low Voltage (at IOL)
VOL
——
0.4
V
Output source current
IOH
4—
—
mA
Output sink current
IOL
4—
—
mA
PWM pin output source current3
IOHP
10
—
mA
PWM pin output sink current4
IOLP
16
—
mA
Input capacitance
CIN
—8
—
pF
Output capacitance
COUT
—12
—
pF
VDD supply current
IDDT
5
Run 6
—
126
152
mA
Wait7
—
105
129
mA
Stop
—60
84
mA
Low Voltage Interrupt, external power supply8
VEIO
2.4
2.7
3.0
V
Low Voltage Interrupt, internal power supply9
VEIC
2.0
2.2
2.4
V
Power on Reset10
VPOR
—1.7
2.0
V
1.
Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, ISB0-2, FAULT0B-3, TCS, TCK, TRST, TMS,
TDI, and MSCAN_RX
2.
Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3.
PWM pin output source current measured with 50% duty cycle.
4.
PWM pin output sink current measured with 50% duty cycle.
5.
IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
6.
Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;
measured with all modules enabled.
7.
Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less
than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured
with PLL enabled.
8.
This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD
via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient
conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated).
9.
This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated
unless the external power supply drops below the minimum specified value (3.0V).
10. Power
–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping
up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally
regulated voltage is typically 100mV less than VDD during ramp-up until 2.5V is reached, at which time it self-regulates.
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
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