參數(shù)資料
型號: DSP56F805FV80E
廠商: Freescale Semiconductor
文件頁數(shù): 36/56頁
文件大?。?/td> 0K
描述: IC DSP 80MHZ 64KB FLASH 144LQFP
標準包裝: 60
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 71KB(35.5K x 16)
程序存儲器類型: 閃存
RAM 容量: 2.5K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
Serial Communication Interface (SCI) Timing
56F805 Technical Data, Rev. 16
Freescale Semiconductor
41
Figure 3-24 Quadrature Decoder Timing
3.11 Serial Communication Interface (SCI) Timing
Figure 3-25 RXD Pulse Width
Table 3-15 SCI Timing4
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL 50pF, fOP = 80MHz
Characteristic
Symbol
Min
Max
Unit
Baud Rate1
1.
fMAX is the frequency of operation of the system clock in MHz.
BR
(fMAX*2.5)/(80)
Mbps
RXD2 Pulse Width
2.
The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
RXDPW
0.965/BR
1.04/BR
ns
TXD3 Pulse Width
3.
The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4.
Parameters listed are guaranteed by design.
TXDPW
0.965/BR
1.04/BR
ns
Phase B
(Input)
Phase A
(Input)
PPH
PIN
PHL
RXD
SCI receive
data pin
(Input)
RXDPW
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