參數(shù)資料
型號(hào): DSP56F807VF80E
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 44/60頁(yè)
文件大小: 522K
代理商: DSP56F807VF80E
56F807 Technical Data Technical Data, Rev. 15
44
Freescale Semiconductor
3.11 Analog-to-Digital Converter (ADC) Characteristics
Table 3-16 ADC Characteristics
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, V
REF
= V
DD
-0.3V, ADCDIV = 4, 9, or 14, (for optimal performance),
ADC clock = 4MHz, 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
50pF, f
OP
= 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
ADC input voltages
V
ADCIN
0
1
1.
output code of 0.
For optimum ADC performance, keep the minimum V
ADCIN
value > 25mV. Inputs less than 25mV may convert to a digital
V
REF2
2.
V
DDA
-0.3V.
3.
Measured in 10-90% range.
V
REF
must be equal to or less than V
DDA
and must be greater than 2.7V. For optimal ADC performance, set V
REF
to
V
Resolution
R
ES
12
12
Bits
Integral Non-Linearity
3
INL
+/- 2.5
+/- 4
LSB
4
4.
LSB = Least Significant Bit.
Differential Non-Linearity
DNL
+/- 0.9
+/- 1
LSB
4
Monotonicity
GUARANTEED
ADC internal clock
5
5.
Guaranteed by characterization.
t
AIC
= 1/
f
ADIC
f
ADIC
0.5
5
MHz
Conversion range
R
AD
V
SSA
V
DDA
V
Conversion time
t
ADC
6
t
AIC
cycles
6
6.
Sample time
t
ADS
1
t
AIC
cycles
6
Input capacitance
C
ADI
5
pF
6
Gain Error (transfer gain)
5
E
GAIN
0.93
1.00
1.08
Total Harmonic Distortion
5
THD
60
64
Offset Voltage
5
V
OFFSET
-90
-25
+10
mV
Signal-to-Noise plus Distortion
5
SINAD
55
60
Effective Number of Bits
5
ENOB
9
10
bit
Spurious Free Dynamic Range
5
SFDR
65
70
dB
Bandwidth
BW
100
KHz
ADC Quiescent Current (each dual ADC)
I
ADC
50
mA
V
REF
Quiescent Current (each dual ADC)
I
VREF
12
16.5
mA
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