參數(shù)資料
型號: DSP56F807VF80E
廠商: Freescale Semiconductor
文件頁數(shù): 58/60頁
文件大小: 0K
描述: IC DSP 80MHZ 60K FLASH 160-BGA
標準包裝: 126
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 160-BGA
包裝: 托盤
Product Documentation
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
7
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F807. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices,
Freescale Literature Distribution Centers, or online at http://www.freescale.com.
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
Table 1-1 56F807 Chip Documentation
Topic
Description
Order Number
56800E
Family Manual
Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set
56800EFM
DSP56F801/803/805/807
User’s Manual
Detailed description of memory, peripherals, and
interfaces of the 56F801, 56F803, 56F805, and
56F807
DSP56F801-7UM
56F807
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
DSP56F807
56F807
Errata
Details any chip issues that might be present
56F807E
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
1.
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
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