參數(shù)資料
型號: DSP56F807VF80E
廠商: Freescale Semiconductor
文件頁數(shù): 9/60頁
文件大?。?/td> 0K
描述: IC DSP 80MHZ 60K FLASH 160-BGA
標(biāo)準(zhǔn)包裝: 126
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 160-BGA
包裝: 托盤
Serial Communications Interface (SCI) Signals
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
17
2.10 Serial Communications Interface (SCI) Signals
Table 2-14 Serial Peripheral Interface (SPI) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
MISO
GPIOE6
Input/
Output
Input/Outp
ut
Input
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is MISO.
1
MOSI
GPIOE5
Input/
Output
Input/Outp
ut
Input
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge that the
slave device uses to latch the data.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is MOSI.
1
SCLK
GPIOE4
Input/Outp
ut
Input/Outp
ut
Input
SPI Serial Clock—In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is SCLK.
1
SS
GPIOE7
Input
Input/Outp
ut
Input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is SS.
相關(guān)PDF資料
PDF描述
DSP56F826BU80 IC DSP 80MHZ 64KB FLASH 100LQFP
DSP56F827FG80E IC HYBRID CTRLR 16BIT 128-LQFP
DSPB56362AG120 IC DSP 24BIT AUD 120MHZ 144-LQFP
DSPB56364AF100 IC DSP 24BIT AUD 100MHZ 100-LQFP
DSPB56366AG120 IC DSP 24BIT AUD 120MHZ 144-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F807VF80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC
DSP56F807VF80J 制造商:Freescale Semiconductor 功能描述:DSP 16BIT - Trays
DSP56F826 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56F826-827UM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor Users Manual
DSP56F826-827UM/D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller