參數(shù)資料
型號: DSP56F827FG80
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 47/60頁
文件大小: 811K
代理商: DSP56F827FG80
Quad Timer Timing
56F827 Technical Data, Rev. 12
Freescale Semiconductor
47
Figure 3-26 Slave Mode Clock Timing
3.12 Quad Timer Timing
Table 3-16 Timer Timing
1, 2
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V,
T
A
= –40
°
to
+85
°
C, C
L
< 50pF, f
op
= 80MHz
1.
In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
Timer input period
P
IN
4T+6
ns
Timer input high/low period
P
INHL
2T+3
ns
Timer output period
P
OUT
2T
ns
Timer output high/low period
P
OUTHL
1T
ns
t
THS
t
TSS
t
HS
t
SS
t
RFSWLS
t
RFSWHS
t
RFBLS
t
RFSBHS
t
TXHIS
t
TXNVS
t
FTXVS
t
TXVS
t
TXES
t
FTXES
t
TFSWLS
t
TFSWHS
t
TFSBLS
t
TFSBHS
t
SCKL
t
SCKW
t
SCKH
First Bit
Last Bit
STCK input
STFS (bl) input
STFS (wl) input
STXD
SRCK input
SRFS (bl) input
SRFS (wl) input
SRXD
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