Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Freescale Semico" />
參數(shù)資料
型號: DSPB56725AF
廠商: Freescale Semiconductor
文件頁數(shù): 15/48頁
文件大?。?/td> 0K
描述: DSP 24BIT AUD 250MHZ 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時(shí)鐘速率: 250MHz
非易失內(nèi)存: 外部
芯片上RAM: 112kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
22
47
Start condition hold time
THD;STA
4.0
0.6
μs
48
SCL low period
TLOW
4.7
1.3
μs
49
SCL high period
THIGH
4.0
1.3
μs
50
SCL and SDA rise time7
TR
1000
300
ns
51
SCL and SDA fall time7
TF
—5.0
5.0
ns
52
Data set-up time
TSU;DAT
250
100
ns
53
Data hold time
THD;DAT
0.0
0.0
0.9
μs
54
DSP clock frequency
Filters bypassed
Very Narrow filters enabled
Narrow filters enabled
Wide filters enabled
FOSC
10.6
11.8
13.1
28.5
39.7
61.0
MHz
55
SCL low to data out valid
TVD;DAT
—3.4
0.9
μs
56
Stop condition setup time
TSU;STO
4.0
0.6
μs
57
HREQ in deassertion to last SCL edge (HREQ in
set-up time)
tSU;RQI
0.0
0.0
ns
58
First SCL sampling edge to HREQ output
deassertion2
Filters bypassed
Very Narrow filters enabled
Narrow filters enabled
Wide filters enabled
TNG;RQO
4
× T
C + 30
4
× T
C + 50
4
× T
C + 130
4
× T
C + 230
50.0
70.0
250.0
150.0
50.0
70.0
150.0
250.0
ns
59
Last SCL edge to HREQ output not deasserted2
Filters bypassed
Very Narrow filters enabled
Narrow filters enabled
Wide filters enabled
TAS;RQO
2
× T
C + 30
2
× T
C + 40
2
× T
C + 80
2
× T
C + 130
40
50
90
140
40
50
90
140
ns
Table 10. SHI I2C Protocol Timing (Continued)
Standard I2C
No.
Characteristics1,2,3,4,5
Symbol/
Expression
Standard
Fast-Mode
Unit
Min
Max
Min
Max
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