Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Freescale Semico" />
參數(shù)資料
型號: DSPB56725AF
廠商: Freescale Semiconductor
文件頁數(shù): 24/48頁
文件大?。?/td> 0K
描述: DSP 24BIT AUD 250MHZ 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時鐘速率: 250MHz
非易失內(nèi)存: 外部
芯片上RAM: 112kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
30
Figure 21 shows the GPIO timing diagram.
Figure 21. GPIO Timing
1.2.6
JTAG Timing
Table 13 lists the JTAG timing.
Table 13. JTAG Timing
No.
Characteristics
All Frequencies
Unit
Min
Max
108
TCK frequency of operation (1/(TC × 3); maximum 10 MHz)
10.0
MHz
109
TCK cycle time in Crystal mode
100.0
ns
110
TCK clock pulse width measured at 1.65 V
50.0
ns
111
TCK rise and fall times
3.0
ns
112
Boundary scan input data setup time
15.0
ns
113
Boundary scan input data hold time
24.0
ns
114
TCK low to output data valid
40.0
ns
115
TCK low to output high impedance
40.0
ns
116
TMS, TDI data setup time
5.0
ns
117
TMS, TDI data hold time
25.0
ns
118
TCK low to TDO data valid
44.0
ns
119
TCK low to TDO high impedance
44.0
ns
Note:
1. 0.95 V < VVDD_CORE < 1.05 V and Tj < 100° C, CL = 50 pF
2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
GPIO
(Input)
GPIO
(Output)
Fsys
100
101
102
103
GPIO
(Output)
104
105
106
107
Valid
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