參數(shù)資料
型號： DSPIC30F3013-20I/SP
廠商： Microchip Technology
文件頁數(shù)： 142/161頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 24K 28DIP
產(chǎn)品培訓(xùn)模塊： Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝： 15
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 24KB（8K x 24）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
其它名稱： DSPIC30F301320ISP
2010 Microchip Technology Inc.
DS70139G-page 67
dsPIC30F2011/2012/3012/3013
8.2
Reset Sequence
A Reset is not a true exception because the interrupt
controller is not involved in the Reset process. The
processor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory
location immediately followed by the address target for
the GOTO instruction. The processor executes the GOTO
to the specified address and then begins operation at
the specified target (start) address.
8.2.1
RESET SOURCES
In addition to external Reset and Power-on Reset
(POR), there are six sources of error conditions which
‘trap’ to the Reset vector.
Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer causes a Reset.
Illegal Instruction Trap:
Attempted execution of any unused opcodes
results in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
Trap Lockout:
Occurrence of multiple trap conditions
simultaneously causes a Reset.
8.3
Traps
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 8-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note that many of these trap conditions can only be
detected
when
they
occur.
Consequently,
the
questionable instruction is allowed to complete prior to
trap exception processing. If the user chooses to
recover from the error, the result of the erroneous
action that caused the trap may have to be corrected.
There are eight fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
8.3.1
TRAP SOURCES
The following traps are provided with increasing
priority. However, since all traps can be nested, priority
has little effect.
Math Error Trap:
The math error trap executes under the following four
circumstances:
1.
If an attempt is made to divide by zero, the
divide operation is aborted on a cycle boundary
and the trap is taken.
2.
If enabled, a math error trap is taken when an
arithmetic operation on either accumulator A or
B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
3.
If enabled, a math error trap is taken when an
arithmetic operation on either accumulator A or
B causes a catastrophic overflow from bit 39 and
all saturation is disabled.
4.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap occurs.
Note:
If the user does not intend to take
corrective action in the event of a trap
error condition, these vectors must be
loaded with the address of a default
handler that contains the RESET instruc-
tion. If, on the other hand, one of the vec-
tors containing an invalid address is
called, an address error trap is generated.
相關(guān)PDF資料
PDF描述
PIC18LF6390-I/PT IC PIC MCU FLASH 4KX16 64TQFP
DSPIC30F3013-30I/SP IC DSPIC MCU/DSP 24K 28DIP
DSPIC33FJ32MC202-E/SO IC DSPIC MCU/DSP 32K 28SOIC
52745-0896 CONN FFC 8POS .5MM R/A ZIF SMD
52745-0496 CONN FFC 4POS .5MM R/A ZIF SMD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSPIC30F3013-30I/ML 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Sensor RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPIC30F3013-30I/SO 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Sensor RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPIC30F3013-30I/SO 制造商:Microchip Technology Inc 功能描述:IC DSC 16BIT 24KB 40MHZ 5.5V SOIC-28
DSPIC30F3013-30I/SP 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Sensor RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPIC30F3013-30I/SP 制造商:Microchip Technology Inc 功能描述:16-Bit Digital Signal Controller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*