參數(shù)資料
型號(hào): DSPIC30F3013-20I/SP
廠商: Microchip Technology
文件頁(yè)數(shù): 60/161頁(yè)
文件大小: 0K
描述: IC DSPIC MCU/DSP 24K 28DIP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 15
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 24KB(8K x 24)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
其它名稱(chēng): DSPIC30F301320ISP
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PIC18F46J11 FAMILY
DS39932D-page 182
2011 Microchip Technology Inc.
11.2.4
BUFFERED PARALLEL SLAVE
PORT MODE
Buffered Parallel Slave Port mode is functionally
identical to the legacy PSP mode with one exception,
the implementation of 4-level read and write buffers.
Buffered PSP mode is enabled by setting the INCM bits
in the PMMODEH register. If the INCM<1:0> bits are
set to ‘11’, the PMP module will act as the Buffered
PSP.
When the Buffered mode is active, the PMDIN1L,
PMDIN1H, PMDIN2L and PMDIN2H registers become
the write buffers and the PMDOUT1L, PMDOUT1H,
PMDOUT2L and PMDOUT2H registers become the
read buffers. Buffers are numbered 0 through 3, start-
ing with the lower byte of PMDIN1L to PMDIN2H as the
read buffers and PMDOUT1L to PMDOUT2H as the
write buffers.
11.2.4.1
READ FROM SLAVE PORT
For read operations, the bytes will be sent out
sequentially, starting with Buffer 0 (PMDOUT1L<7:0>)
and ending with Buffer 3 (PMDOUT2H<7:0>) for every
read strobe. The module maintains an internal pointer
to keep track of which buffer is to be read. Each buffer
has a corresponding read status bit, OBxE, in the
PMSTATL register. This bit is cleared when a buffer
contains data that has not been written to the bus, and
is set when data is written to the bus. If the current buf-
fer location being read from is empty, a buffer underflow
is generated, and the Buffer Overflow flag bit, OBUF, is
set. If all four OBxE status bits are set, then the Output
Buffer Empty flag (OBE) will also be set.
11.2.4.2
WRITE TO SLAVE PORT
For write operations, the data has to be stored
sequentially, starting with Buffer 0 (PMDIN1L<7:0>)
and ending with Buffer 3 (PMDIN2H<7:0>). As with
read operations, the module maintains an internal
pointer to the buffer that is to be written next.
The input buffers have their own write status bits, IBxF
in the PMSTATH register. The bit is set when the buffer
contains unread incoming data, and cleared when the
data has been read. The flag bit is set on the write
strobe. If a write occurs on a buffer when its associated
IBxF bit is set, the Buffer Overflow flag, IBOV, is set;
any incoming data in the buffer will be lost. If all four
IBxF flags are set, the Input Buffer Full Flag (IBF) is set.
In Buffered Slave mode, the module can be configured
to generate an interrupt on every read or write strobe
(IRQM<1:0> = 01). It can be configured to generate an
interrupt on a read from Read Buffer 3 or a write to
Write Buffer 3, which is essentially an interrupt every
fourth read or write strobe (RQM<1:0> = 11). When
interrupting every fourth byte for input data, all input
buffer registers should be read to clear the IBxF flags.
If these flags are not cleared, then there is a risk of
hitting an overflow condition.
FIGURE 11-5:
PARALLEL MASTER/SLAVE CONNECTION BUFFERED EXAMPLE
PMD<7:0>
PMRD
PMWR
PMCS
Data Bus
Control Lines
PMRD
PMWR
PIC18 Slave
PMCS
PMDOUT1L (0)
PMDOUT1H (1)
PMDOUT2L (2)
PMDOUT2H (3)
PMDIN1L (0)
PMDIN1H (1)
PMDIN2L (2)
PMDIN2H (3)
PMD<7:0>
Write
Address
Pointer
Read
Address
Pointer
Master
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DSPIC30F3013-30I/SP 制造商:Microchip Technology Inc 功能描述:16-Bit Digital Signal Controller