參數(shù)資料
型號: DSPIC30F3013-20I/SP
廠商: Microchip Technology
文件頁數(shù): 93/161頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 24K 28DIP
產(chǎn)品培訓模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝: 15
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 24KB(8K x 24)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
其它名稱: DSPIC30F301320ISP
dsPIC30F2011/2012/3012/3013
DS70139G-page 22
2010 Microchip Technology Inc.
2.3
Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit signed and unsigned integer divide opera-
tions, in the form of single instruction iterative divides.
The
following
instructions
and
data
sizes
are
supported:
1.
DIVF
- 16/16 signed fractional divide
2.
DIV.sd
- 32/16 signed divide
3.
DIV.ud
- 32/16 unsigned divide
4.
DIV.s
- 16/16 signed divide
5.
DIV.u
- 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The divide instructions must be executed within a
REPEAT
loop.
Any
other
form
of
execution
(e.g., a series of discrete divide instructions) will not
function correctly because the instruction flow depends
on
RCOUNT.
The
divide
instruction
does
not
automatically set up the RCOUNT value and it must,
therefore, be explicitly and correctly specified in the
REPEAT
instruction, as shown in Table 2-1 (REPEAT
executes the target instruction {operand value+1}
times). The REPEAT loop count must be setup for 18
iterations of the DIV/DIVF instruction. Thus, a
complete divide operation requires 19 cycles.
TABLE 2-1:
DIVIDE INSTRUCTIONS
Note:
The divide flow is interruptible; however,
the user needs to save the context as
appropriate.
Instruction
Function
DIVF
Signed fractional divide: Wm/Wn
→W0; Rem →W1
DIV.sd
Signed divide: (Wm+1:Wm)/Wn
→W0; Rem →W1
DIV.s
Signed divide: Wm/Wn
→W0; Rem →W1
DIV.ud
Unsigned divide: (Wm+1:Wm)/Wn
→W0; Rem →W1
DIV.u
Unsigned divide: Wm/Wn
→W0; Rem →W1
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