參數(shù)資料
型號： DSPIC33FJ12MC201T-I/SS
廠商： Microchip Technology
文件頁數(shù)： 113/155頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 12K 20SSOP
產(chǎn)品培訓模塊： Asynchronous Stimulus
標準包裝： 1,600
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，SPI，UART/USART
外圍設備： 高級欠壓探測/復位，電機控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 15
程序存儲器容量： 12KB（12K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 4x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
配用： DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱： DSPIC33FJ12MC201T-I/SSTR
60
A/T89C51AC2
4127H–8051–02/08
Timer 1
Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The fol-
lowing comments help to understand the differences:
Timer 1 functions as either a Timer or event Counter in three modes of operation.
Figure 31 to Figure 33 show the logical configuration for modes 0, 1, and 2. Timer
1’s mode 3 is a hold-count mode.
Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 40)
and bits 2, 3, 6 and 7 of TCON register (see Figure 39). TMOD register selects the
method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of
operation (M11 and M01). TCON register provides Timer 1 control functions:
overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type
control bit (IT1).
Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best
suited for this purpose.
For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented
by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control
Timer operation.
Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating
an interrupt request.
When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit
(TR1). For this situation, use Timer 1 only for applications that do not require an
interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in
and out of mode 3 to turn it off and on.
It is important to stop Timer/Counter before changing mode.
Mode 0 (13-bit Timer)
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-
ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register
(see Figure 31). The upper 3 bits of TL1 register are ignored. Prescaler overflow incre-
ments TH1 register.
Mode 1 (16-bit Timer)
Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in
cascade (see Figure 32). The selected input increments TL1 register.
Mode 2 (8-bit Timer with Auto-
Reload)
Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from
TH1 register on overflow (see Figure 33). TL1 overflow sets TF1 flag in TCON register
and reloads TL1 with the contents of TH1, which is preset by software. The reload
leaves TH1 unchanged.
Mode 3 (Halt)
Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt
Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
Interrupt
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This
flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer
interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes
interrupts are globally enabled by setting EA bit in IEN0 register.
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