參數(shù)資料
型號: DSPIC33FJ12MC201T-I/SS
廠商: Microchip Technology
文件頁數(shù): 71/155頁
文件大小: 0K
描述: IC DSPIC MCU/DSP 12K 20SSOP
產(chǎn)品培訓模塊: Asynchronous Stimulus
標準包裝: 1,600
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,SPI,UART/USART
外圍設備: 高級欠壓探測/復位,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱: DSPIC33FJ12MC201T-I/SSTR
2010 Microchip Technology Inc.
DS41303G-page 297
PIC18F2XK20/4XK20
22.5
Applications
In many applications, the ability to detect a drop below,
or rise above, a particular threshold is desirable. For
example, the HLVD module could be periodically
enabled to detect Universal Serial Bus (USB) attach or
detach. This assumes the device is powered by a lower
voltage source than the USB when detached. An attach
would indicate a high-voltage detect from, for example,
3.3V to 5V (the voltage on USB) and vice versa for a
detach. This feature could save a design a few extra
components and an attach signal (input pin).
For general battery applications, Figure 22-4 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage
VA, the HLVD logic generates an interrupt at time TA.
The interrupt could cause the execution of an ISR,
which
would
allow
the
application
to
perform
“housekeeping
tasks”
and
perform
a
controlled
shutdown before the device voltage exits the valid
operating range at TB. The HLVD, thus, would give the
application a time window, represented by the
difference between TA and TB, to safely exit.
FIGURE 22-4:
TYPICAL LOW-VOLTAGE
DETECT APPLICATION
TABLE 22-1:
REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Time
Vo
lt
a
g
e
VA
VB
TA
TB
VA = HLVD trip point
VB = Minimum valid device
operating voltage
Legend:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
HLVDCON
VDIRMAG
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
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