參數(shù)資料
型號： DSPIC33FJ12MC201T-I/SS
廠商： Microchip Technology
文件頁數(shù)： 55/155頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 12K 20SSOP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 1,600
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，SPI，UART/USART
外圍設(shè)備： 高級欠壓探測/復(fù)位，電機(jī)控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 15
程序存儲器容量： 12KB（12K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
配用： DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱： DSPIC33FJ12MC201T-I/SSTR
PIC18F2XK20/4XK20
DS41303G-page 282
2010 Microchip Technology Inc.
20.4
Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusive-
or gate (see Figure 20-2 and Figure 20-3). One latch is
updated with the comparator output level when the
CMxCON0 register is read. This latch retains the value
until the next read of the CMxCON0 register or the
occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMxCON0 register is read or the comparator
output returns to the previous state.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the inter-
rupt flag can be reset without the additional step of
reading or writing the CMxCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred. See Figures 20-4
and 20-5.
The CxIF bit of the PIR2 register is the comparator
interrupt flag. This bit must be reset by software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, an interrupt can be generated.
In mid-range Compatibility mode the CxIE bit of the
PIE2 register and the PEIE and GIE bits of the INTCON
register must all be set to enable comparator interrupts.
If any of these bits are cleared, the interrupt is not
enabled, although the CxIF bit of the PIR2 register will
still be set if an interrupt condition occurs.
20.4.1
PRESETTING THE MISMATCH
LATCHES
The comparator mismatch latches can be preset to the
desired state before the comparators are enabled.
When the comparator is off the CxPOL bit controls the
CxOUT level. Set the CxPOL bit to the desired CxOUT
non-interrupt level while the CxON bit is cleared. Then,
configure the desired CxPOL level in the same instruc-
tion that the CxON bit is set. Since all register writes are
performed as a Read-Modify-Write, the mismatch
latches will be cleared during the instruction Read
phase and the actual configuration of the CxON and
CxPOL bits will be occur in the final Write phase.
FIGURE 20-4:
COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
FIGURE 20-5:
COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
2: Comparator interrupts will operate correctly
regardless of the state of CxOE.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read oper-
ation is being executed (start of the Q2
cycle), then the CxIF interrupt flag of the
PIR2 register may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is stable.
Allow about 1
s for bias settling then clear
the mismatch condition and interrupt flags
before enabling comparator interrupts.
Q1
Q3
CxIN+
CxOUT
Set CxIF (edge)
CxIF
TRT
reset by software
Q1
Q3
CxIN+
CxOUT
Set CxIF (edge)
CxIF
TRT
reset by software
cleared by CMxCON0 read
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