參數(shù)資料
型號: DSPIC33FJ12MC201T-I/SS
廠商: Microchip Technology
文件頁數(shù): 79/155頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 12K 20SSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 1,600
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,SPI,UART/USART
外圍設(shè)備: 高級欠壓探測/復(fù)位,電機(jī)控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱: DSPIC33FJ12MC201T-I/SSTR
2010 Microchip Technology Inc.
DS41303G-page 303
PIC18F2XK20/4XK20
REGISTER 23-4:
CONFIG3H: CONFIGURATION REGISTER 3 HIGH
R/P-1
U-0
R/P-1
R/P-0
R/P-1
MCLRE
HFOFST
LPT1OSC
PBADEN
CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
x = Bit is unknown
bit 7
MCLRE: MCLR Pin Enable bit
1
= MCLR pin enabled; RE3 input pin disabled
0
= RE3 input pin enabled; MCLR disabled
bit 6-4
Unimplemented: Read as ‘0’
bit 3
HFOFST: HFINTOSC Fast Start-up
1
= HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize.
0
= The system clock is held off until the HFINTOSC is stable.
bit 2
LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1
= Timer1 configured for low-power operation
0
= Timer1 configured for higher power operation
bit 1
PBADEN: PORTB A/D Enable bit
(Affects ANSELH Reset state. ANSELH controls PORTB<4:0> pin configuration.)
1
= PORTB<4:0> pins are configured as analog input channels on Reset
0
= PORTB<4:0> pins are configured as digital I/O on Reset
bit 0
CCP2MX: CCP2 MUX bit
1
= CCP2 input/output is multiplexed with RC1
0
= CCP2 input/output is multiplexed with RB3
REGISTER 23-5:
CONFIG4L: CONFIGURATION REGISTER 4 LOW
R/P-1
R/P-0
U-0
R/P-1
U-0
R/P-1
DEBUG
XINST
—LVP(1)
STVREN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
x = Bit is unknown
bit 7
DEBUG: Background Debugger Enable bit
1
= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0
= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6
XINST: Extended Instruction Set Enable bit
1
= Instruction set extension and Indexed Addressing mode enabled
0
= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5-3
Unimplemented: Read as ‘0’
bit 2
LVP: Single-Supply ICSP Enable bit
1
= Single-Supply ICSP enabled
0
= Single-Supply ICSP disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
STVREN: Stack Full/Underflow Reset Enable bit
1
= Stack full/underflow will cause Reset
0
= Stack full/underflow will not cause Reset
Note
1:
Can only be changed by a programmer in high-voltage programming mode.
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