參數(shù)資料
型號(hào)： ICS1894KI-32LF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 48/50頁(yè)
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 32QFN
標(biāo)準(zhǔn)包裝： 490
類型： PHY 收發(fā)器
規(guī)程： MII，RMII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 托盤
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
7
ICS1894-32
REV M 021512
The MIIM interface consists of the following:
A physical connection that incorporates the clock line
(MDC) and the data line (MDIO).
A specific protocol that operates across the
aforementioned physical connection that allows an
external controller to communicate with one or more
ICS1894-32 devices. Each ICS1894-32 device is
assigned a PHY address between 1 and 7 by the P[4:0]
strapping pins. P3 and P4 address bits are hardcoded to
‘0’ in design.
An internal addressable set of thirty-one 8-bit MDIO
registers. Register [0:6] are required, and their functions
are defined by the IEEE 802.3u Specification. The
additional registers are provided for expanded
functionality.
The ICS1894-32 supports MIIM in both MII mode and RMII
mode.
The following table shows the MII Management frame
format for the ICS1894-32.
MII Management Frame Format
Interrupt (INT)
P2/INT (pin 11) is an optional interrupt signal that is used to
inform the external controller that there has been a status
update in the ICS1894-32 PHY register. Register 23 shows
the status of the various interrupts while register 22 controls
the enabling/disabling of the interrupts.
MII Data Interface
The Media Independent Interface (MII) is specified in
Clause 22 of the IEEE 802.3u Specification. It provides a
common interface between physical layer and MAC layer
devices, and has the following key characteristics:
Supports 10Mbps and 100Mbps data rates.
Uses a 25MHz reference clock, sourced by the PHY.
Provides independent 4-bit wide (nibble) transmit and
receive data paths.
Contains two distinct groups of signals: one for
transmission and the other for reception.
The ICS1894-32 is configured for MII mode upon power-up
or hardware reset with the following:
A 25MHz crystal connected to REFIN, REFOUT (pins 30,
29), or an external 25MHz clock source (oscillator)
connected to REFIN
Preamble Start of
Frame
Read/Write
OP Code
PHY Address
Bits [4:0]
REG Address
Bits [4:0]
TA
Data Bits
[15:0]
Idle
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
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參數(shù)描述
ICS1894KI-32LFT 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 產(chǎn)品培訓(xùn)模塊:RS-232 & USB Transceiver 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:296-19849-2
ICS1894KI-33LF 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN
ICS1894KI-33LFT 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN
ICS1894KI-34LF 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN
ICS1894KI-34LFT 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN
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