參數(shù)資料
型號(hào): ICS1894KI-32LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 29/50頁
文件大?。?/td> 0K
描述: PHYCEIVER LOW PWR 3.3V 32QFN
標(biāo)準(zhǔn)包裝: 490
類型: PHY 收發(fā)器
規(guī)程: MII,RMII
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
35
ICS1894-32
REV M 021512
100M MII: Synchronous Transmit Timing
The table below lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time
periods consist of timings of signals on the following pins:
TXCLK
TXD[3:0]
TXEN
TXER
The 100M MII/100M Stream Interface Synchronous Transmit Timing Diagram figure shows the timing diagram for
the time periods.
100M MII/100M Stream Interface Synchronous Transmit Timing Diagram
10M MII: Synchronous Transmit Timing
The table below lists the significant time periods for the 10M MII synchronous transmit timing. The time periods
consist of timings of signals on the following pins:
TXCLK
TXD[3:0]
TXEN
TXER
The 10M MII Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods.
Time
Period
Parameter
Conditions
Min.
Typ.
Max. Units
t1
TXD[3:0], TXEN, TXER Setup to TXCLK Rise
15
ns
t2
TXD[3:0], TXEN, TXER Hold after TXCLK Rise
0
ns
t1
t2
TXCLK
TXD[3:0]
TXEN
TXER
Time
Period
Parameter
Conditions
Min.
Typ.
Max. Units
t1
TXD[3:0], TXEN, TXER Setup to TXCLK Rise
375
ns
t2
TXD[3:0], TXEN, TXER Hold after TXCLK Rise
0
ns
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