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參數(shù)資料
| 型號： | ICS1894KI-32LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 23/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 32QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII，RMII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 托盤 |
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ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
3
ICS1894-32
REV M 021512
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type1
Pin Description
1
TP_AP
AIO
Twisted pair port A (for either transmit or receive) positive signal
2
TP_AN
AIO
Twisted pair port A (for either transmit or receive) negative signal
3
VSS
Ground Connect to ground.
4
VDD
Power
3.3V Power Supply
5
TP_BN
AIO
Twisted pair port B (for either transmit or receive) negative signal
6
TP_BP
AIO
Twisted pair port B (for either transmit or receive) positive signal
7
VDD
Power
3.3V Power Supply
8
TCSR
AIO
Transmit Current bias pin, connected to Vdd and ground via resistors (see
“Recommended Component Values” table and the “ICS1894-32 TCSR” figure).
9
VSS
Ground Connect to ground.
10
RESET_N
Input
Hardware reset for the entire chip (active low)
11
P2/INT
IO/Ipd
PHY address Bit 2 as input (during power on reset/hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
12
MDIO
IO
Management Data Input/Output
13
MDC
Input
Management Data Clock
14
AMDIX/RXD3
IO/Ipu
AMDIX enable as input (during power on reset/hardware reset)
Receive data Bit 3 in MII mode as output.
15
P3/RXD2
IO/Ipd
PHY address Bit 3 as input (during power on reset/hardware reset)
Receive data Bit 2 in MII mode as output.
16
RXTRI/
RXD1
IO/Ipd
RX tri-state enable as input (during power on reset/hardware reset)
Receive data Bit 1 in both RMII and MII mode as output.
17
FDPX/
RXD0
IO/Ipu
Full duplex enable as input (during power on reset/hardware reset)
Receive data Bit 0 in both RMII and MII mode as output
18
RMII/RXDV
IO/Ipd
RMII/MII select as input (during power on reset/hardware reset)
Receive data valid in MII mode and CRS_DV in RMII mode as output.
19
VDDIO
Power
3.3 V/1.8 V IO Power Supply.
20
ANSEL/
RXCLK
IO/Ipu
Auto-negotiation enable as input (during power on reset/hardware reset)
Receive clock in MII mode as output.
21
NOD/
RXER
IO/Ipd
Node select as input (during power on reset/hardware reset)
Receive error in MII/RMII mode as output
It is recommended to always pull this pin low on power-up or hardware reset.
22
SPEED/
TXCLK
IO/Ipu
10M/100M select as input (during power on reset/hardware reset)
Transmit clock in MII mode as output
23
TXEN
Input
Transmit enable in RMII/MII mode
24
TXD0
Input
Transmit data Bit 0 in RMII/MII mode
25
VDDD
Power
3.3 V Power Supply
26
TXD1
Input
Transmit data Bit 1 in RMII/MII mode
27
TXT2
Input
Transmit data Bit 2 in MII mode
28
TXD3
Input
Transmit data Bit 3 in MII mode
29
REFOUT
Output
25 MHz crystal output, floating in RMII mode
30
REFIN
Input
25 MHz crystal (or clock) input in MII mode. 50 MHz clock input in RMII mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1894KI-32LFT | 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 產(chǎn)品培訓(xùn)模塊:RS-232 & USB Transceiver 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):1/1 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:296-19849-2 |
| ICS1894KI-33LF | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-33LFT | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-34LF | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-34LFT | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
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