參數(shù)資料
型號(hào): ICS1894KI-32LF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 28/50頁(yè)
文件大?。?/td> 0K
描述: PHYCEIVER LOW PWR 3.3V 32QFN
標(biāo)準(zhǔn)包裝: 490
類(lèi)型: PHY 收發(fā)器
規(guī)程: MII,RMII
電源電壓: 3.14 V ~ 3.47 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(pán)(5x5)
包裝: 托盤(pán)
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
34
ICS1894-32
REV M 021512
Timing for Transmit Clock (TXCLK) Pin
The table below lists the significant time periods for signals on the Transmit Clock (TXCLK) pin. The Transmit Clock
Timing Diagram figure shows the timing diagram for the time periods.
Transmit Clock Timing Diagram
Timing for Receive Clock (RXCLK) Pin
The table below lists the significant time periods for signals on the Receive Clock (RXCLK) pin. The Receive Clock
Timing Diagram figure shows the timing diagram for the time periods.
Receive Clock Timing Diagram
Time
Period
Parameter
Conditions
Min. Typ. Max.
Units
t1
TXCLK Duty Cycle
35
50
65
%
t2a
TXCLK Period
100M MII (100Base-TX)
40
ns
t2b
TXCLK Period
10M MII (10Base-T)
400
ns
t1
t2x
TXCLK
Time
Period
Parameter
Conditions
Min. Typ. Max. Units
t1
RXCLK Duty Cycle
35
50
65
%
t2a
RXCLK Period
100M MII (100Base-TX)
40
ns
t2b
RXCLK Period
10M MII (10Base-T)
400
ns
RXCLK
t1
t2
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參數(shù)描述
ICS1894KI-32LFT 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器,接收器,收發(fā)器 系列:PHYceiver™ 產(chǎn)品培訓(xùn)模塊:RS-232 & USB Transceiver 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SSOP(0.209",5.30mm 寬) 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):296-19849-2
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