參數(shù)資料
型號： DZPD6710VCB
廠商： INTEL CORP
元件分類： 總線控制器
英文描述： ISA-to-PC-Card (PCMCIA) Controllers
中文描述： PCMCIA BUS CONTROLLER, PQFP144
封裝： LQFP-144
文件頁數(shù)： 66/138頁
文件大?。?/td> 723K
代理商： DZPD6710VCB
PD6710/
’
22
—
ISA-to-PC-Card (PCMCIA) Controllers
66
Datasheet
9.3
System Memory Map 0
–
4 End Address Low
There are five separate System Memory Map End Address Low registers, each with identical
fields. These registers are located at the following indexes:
Index
12h
1Ah
22h
2Ah
32h
System Memory Map End Address Low
System Memory Map 0 End Address Low
System Memory Map 1 End Address Low
System Memory Map 2 End Address Low
System Memory Map 3 End Address Low
System Memory Map 4 End Address Low
Bits 7:0
—
End Address 19:12
This register contains the least-significant byte of the address that specifies where in the memory
space the corresponding memory map will end. Memory accesses that are equal or below this
address and equal or above the corresponding System Memory Map Start Address will be mapped
into the memory space of the corresponding PC Card.
The most-significant four bits are located in the
System Memory Map 0
–
4 End Address High
register (see
“
System Memory Map 0
–
4 End Address High
”
on page 66
).
9.4
System Memory Map 0
–
4 End Address High
There are five separate System Memory Map End Address High registers, each with identical
fields. These registers are located at the following indexes:
Index
13h
1Bh
System Memory Map End Address High
System Memory Map 0 End Address High
System Memory Map 1 End Address High
Register Name:
System Memory Map 0
–
4 End Address Low
Index:
12h, 1Ah, 22h, 2Ah, 32h
Bit 7
Bit 6
Register Per:
socket
Register Compatibility Type:
365
Bit 1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 0
End Address 19:12
RW:00000000
Register Name:
System Memory Map 0
–
4 End Address High
Index:
13h, 1Bh, 23h, 2Bh, 33h
Register Per:
socket
Register Compatibility Type:
365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Card Timer Select
Scratchpad Bits
End Address 23:20
RW:00
RW:00
RW:0000
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