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參數(shù)資料
| 型號： | DZPD6710VCB |
| 廠商： | INTEL CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | ISA-to-PC-Card (PCMCIA) Controllers |
| 中文描述： | PCMCIA BUS CONTROLLER, PQFP144 |
| 封裝： | LQFP-144 |
| 文件頁數(shù)： | 92/138頁 |
| 文件大?。?/td> | 723K |
| 代理商： | DZPD6710VCB |
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PD6710/
’
22
—
ISA-to-PC-Card (PCMCIA) Controllers
92
Datasheet
Bit 5 allows programming of the active level of GPSTB, with the default being active-low. Setting
bit 5 to
‘
1
’
causes a GPSTB output to be low normally and high (active) upon external data access.
Bit 4 controls use of the respective GPSTB pin as a write strobe for an external general-purpose
latch. When the respective extended index is set to 0Ah and the index register is set to the
respective 2Fh or 6Fh setting, I/O writes that access address 3E1h will result in the respective
GPSTB signal being driven active for the duration of the ISA bus IOW* signal being driven low.
Bit 3 controls use of the respective GPSTB pin a read strobe for an external general-purpose buffer.
When the respective extended index is set to 0Ah and the index register is set to the respective 2Fh
or 6Fh setting, I/O reads that access address 3E1h will result in the respective GPSTB signal being
driven active for the duration of the ISA bus IOR* signal being driven low.
Bit 2 cause the GPSTB output to be totem-pole instead of the default open-collector configuration.
When GPSTB outputs are totem-pole, their
‘
high
’
level is driven to the voltage of the
‘
+5V
’
pin,
instead of to high-impedance.
If neither bit 3 nor bit 4 is set, the respective GPSTB pin functions as a reserved input in a PD6722
that is an internal pull-up to the
‘
+5V
’
pin. This internal pull-up is turned off whenever the GPSTB
pin is configured as a general-purpose strobe, or when the respective socket
’
s Pull-up Control bit is
set to
‘
1
’
.
Bits 7:6 and 1:0 are reserved and
must
be programmed to
‘
0
’
. These bits should not be used as
scratchpad bits.
External Data Port Access through the External Data Register
Data to be accessed from an external read or write port is mapped to the respective
External Data
register at Extended Index 0Ah. This allows external data to be accessed as if it were a register in
the PD67XX register set.
To achieve this mapping, the external data port
’
s buffer or latch data connections should be made to
SD[15:8] of the system bus for 16-bit systems, and to SD[7:0] of the system bus for 8-bit systems.
To support readback of data written to an external I/O port by use of a GPSTB pin, a shadow of the
external data register exists, which is read when an I/O read is done from the external data register
location corresponding to a GPSTB pin programmed as a write strobe.
For more information on the Socket A and Socket B versions of this register, see the description of
this register in
“
External Data (PD6722 only, Socket A, Index 2Fh)
”
on page 81
and
“
External Data
(PD6722 only, Socket A, Index 6Fh)
”
on page 82
.
Register Name:
External Data
Index:
2Fh
Extended Index:
0Ah
Register Per:
socket
Register Compatibility Type:
ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Data
7
External Data
6
External Data
5
External Data
4
External Data
3
External Data
2
External Data
1
External Data
0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
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