參數(shù)資料
型號: DZPD6710VCB
廠商: INTEL CORP
元件分類: 總線控制器
英文描述: ISA-to-PC-Card (PCMCIA) Controllers
中文描述: PCMCIA BUS CONTROLLER, PQFP144
封裝: LQFP-144
文件頁數(shù): 93/138頁
文件大?。?/td> 723K
代理商: DZPD6710VCB
ISA-to-PC-Card (PCMCIA) Controllers
PD6710/
22
Datasheet
93
13.2
Example Implementations of GPSTB-Controlled Read and
Write Ports
In this mode,
Extension Control 2
register bit 4 is set to
1
enabling the GPSTB pin to function as
a write strobe. Writes to the respective extended index 0Ah cause the respective GPSTB to go
active (low) for the duration of the system
s IOW* pulse.
On writes, data is written to both the external latch and the internal shadow copy of the
External
Data
register. A read of the respective extended index 0Ah would produce the last value written to
the latch.
Connection of the ISA bus PWRGOOD signal to the external latch ensures that the latch assumes
all
0
s at its outputs when the PD67XX is reset.
Figure 13. Example GPSTB Write Port (Extension Control 2 bits 4:3 are
10
)
IOW*
IOW*
SD[15:0]
SD[15:0]
GPSTB
Latch
CK
O0
D
RES
EXT_WR*
SD[15:8]
(16-bit bus)
General-
Purpose
Outputs
O7
PWRGOOD
Pull-up
Pull-up resistor, or set Extension Control 2 bit 2 to
1
for totem-pole output.
(for example,
374)
PD6722
Figure 14. Example GPSTB Read Port (Extension Control 2 bits 4:3 are
01
)
IOR*
IOR*
SD[15:0]
SD[15:0]
GPSTB
Tristate Buffer
(for example,
244)
D7
O
D0
OE
EXT_RD*
SD[15:8]
(16-bit bus)
General-
Purpose
Inputs
Pull-up resistor, or set Extension Control 2 bit 2 to
1
for totem-pole output.
Pull-up
PD6722
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