![](http://datasheet.mmic.net.cn/190000/E0C88F360F_datasheet_14901875/E0C88F360F_7.png)
7
E0C88F360
q Initial Reset
E0C88F360 uses the initial reset signal as a trigger for setting either the normal operation mode or the program-
ming mode. Therefore, design the reset input circuit so that the IC will be reset for sure. When resetting the IC in
the normal operation mode, make sure to fix the XSPRG terminal at High level.
q ROM
The E0C88F360 employs a Flash EEPROM for the internal ROM. The ROM has a capacity of 61,440
× 8 bits and
is allocated to 000000H–00EFFFH. The Flash EEPROM can be rewritten up to 1,000 times. Rewriting data is
done at the user's own risk.
q RAM
The built-in RAM has a capacity of 2,048 words
× 8 bits and is allocated to 00F000H–00F7FFH.
q Oscillation Circuit
In the E0C88F360, only crystal oscillator is available for the OSC1 oscillation circuit and either CR or crystal/
ceramic oscillator is available for the OSC3 oscillation circuit. Furthermore, pay attention to the difference on the
oscillation start time according to the supply voltage. Be sure to have enough margin especially for stabilizing the
OSC3 oscillation when controlling the peripheral circuit that uses the OSC3 clock.
q SVD Circuit
The E0C88F360 has a built-in SVD circuit.
Detection level
Level 1
→ Level 0
Level 2
→ Level 1
Level 3
→ Level 2
Level 4
→ Level 3
Level 5
→ Level 4
Level 6
→ Level 5
Level 7
→ Level 6
Level 8
→ Level 7
Level 9
→ Level 8
Level 10
→ Level 9
Level 11
→ Level 10
Level 12
→ Level 11
Level 13
→ Level 12
Level 14
→ Level 13
Level 15
→ Level 14
Min.
Typ.
× 0.92
Typ.
× 0.88
E0C883xx/888xx
Typ.
1.82
2.00
2.18
2.36
2.54
2.72
2.90
3.08
3.26
3.45
3.65
3.85
4.05
4.25
4.50
Max.
Typ.
× 1.08
Typ.
× 1.12
(Unit: V)
Min.
Typ.
× 0.92
Typ.
× 0.88
E0C883F360
Typ.
1.82
2.00
2.18
2.36
2.54
2.72
2.90
3.08
3.26
3.45
3.65
3.85
4.05
4.25
4.50
Max.
Typ.
× 1.08
Typ.
× 1.12
The mask option for reseting when low voltage is detected (available in the E0C88xxx) is not provided in the
E0C88F360.