
12
E0C88F360
Analog comparator
Note)
9
10
11
When "no pull-up resistor" (comparator input terminal) is selected by mask option.
Stability time is the time from turning the circuit ON until the circuit is stabilized.
Response time is the time that the output result responds to the input signal.
(Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=25
°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Condition
Analog comparator
operating voltage input range
Analog comparator
offset voltage
Analog comparator stability time
Analog comparator
response time
VCMIP
VCMIM
VCMOF
tCMP1
tCMP2
0.7
VDD - 0.7
20
1
2
V
mV
mS
Non-inverted input (CMPP)
Inverted input (CMPM)
VCMIP = 0.7V to VDD - 0.7V
VCMIM = 0.7V to VDD - 0.7V
VCMIP = 0.7V to VDD - 0.7V
VCMIM = 0.7V to VDD - 0.7V
VCMIP = VCMIM
± 0.025V
Note
9
10
11
A/D converter
Zero-scale error:
Ezs = deviation from the ideal value at zero point
Full-scale error:
Efs = deviation from the ideal value at the full scale point
Non-linearity error: El = deviation of the real conversion curve from the end point line
Total error:
Et = max(Ezs, Efs, Eabs), Eabs = deviation from the ideal line (including quantization error)
(Unless otherwise specified: VDD=AVDD=AVREF=5.0V, VSS=AVSS=0V, fOSC1=32.768kHz, fOSC3=4.0MHz, Ta=25
°C)
Symbol
Min.
Typ.
Max.
Unit
Zero-scale error
Full-scale error
Non-linearity error
Total error
A/D converter
current consumption
Input clock frequency
Ezs
Efs
El
Et
IAD
f
-1.50
-3.00
0.50
1.80
2
1.50
3.00
1.00
3.50
4
LSB
mA
MHz
VDD=AVDD=AVREF=2.7 to 5.5V,
ADCLK=2MHz, Ta=25
°C
VDD=AVDD=AVREF=3.0V, ADCLK=2MHz, Ta=25
°C
AVREF and ADCLK divider current not included
VDD=AVDD=AVREF=5.0V, ADCLK=2MHz, Ta=25
°C
AVREF and ADCLK divider current not included
VDD=AVDD=AVREF=2.7 to 5.5V, Ta=25
°C
Note
Item
Condition
q Power Current Consumption (The table shows objective values, so they may be changed.)
Item
Symbol
Min.
Typ.
Max.
Unit
Condition
Power current
(Normal mode)
Power current
(High-speed mode)
Power current
(Low-power mode)
LCD drive circuit current
SVD circuit current
Analog comparator
circuit current
IDD1
IDD2
IDD3
IDD4
IHVL
IDD1
IDD2
IDD3
IDD4
IHVL
IDD1
IDD2
IDD3
IHVL
ILCDN
ILCDH
ISVDN
ISVDH
ICMP1
ICMP2
3
18
0.5
32
1
10
1
5
25
1
70
3
10
40
2
100
1
5
16
40
8
35
180
240
100
10
A
mA
A
mA
A
In SLEEP status
In HALT status
CPU is in RUN status (VDD = 5.5V, 32.768kHz)
CPU is in RUN status (VDD = 5.5V, 1MHz)
In heavy load protection mode
In SLEEP status
In HALT status
CPU is in RUN status (VDD = 5.5V, 32.768kHz)
CPU is in RUN status (VDD = 5.5V, 1MHz)
In heavy load protection mode
In SLEEP status
In HALT status
CPU is in RUN status (VDD = 3.5V, 32.768kHz)
In heavy load protection mode
VDD = 5.5V
In heavy load protection mode
VDD = 5.5V
In heavy load protection mode
CMPXDT="1"
CMPXDT="0"
Note
12
13
12
#
1
#
2
#
3
#
4
12
13
#
(Unless otherwise specified: VDD=Within the operating voltage in each operating mode, VSS=0V, Ta=25
°C,
OSC1=32.768kHz crystal oscillation, CG=25pF, OSC3=External clock input, Non heavy load protection mode, C1–C9=0.1
F, No panel load)
OSC1: Stop,
OSC1: Oscillating,
It is the value of current which flows in the heavy load protection circuit when in the heavy load protection mode (OSC3 ON or buzzer ON).
The value when VDD = x V can be found by the following expression: ISVDN (VDD = x V) = (x
× 60) - 150 (Max. value)
In the E0C88F360, CR option cannot be selected for the OSC1 oscillation circuit.
#1
#2
#3
#4
#1
#2
#3
#4
#1
#2
#3
Note)
OSC3: Stop,
OSC3: Oscillating,
CPU, ROM, RAM: SLEEP status,
CPU, ROM, RAM: HALT status,
CPU, ROM, RAM: Runing in 32.768kHz,
CPU, ROM, RAM: Runing in 1MHz,
Clock timer: Stop,
Clock timer: Runing,
Others: Stop status