參數(shù)資料
型號： EDD5116AFTA-7B-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits DDR SDRAM
中文描述： 32M X 16 DDR DRAM, 0.75 ns, PDSO66
封裝： ROHS COMPLIANT, PLASTIC, TSOP2-66
文件頁數(shù)： 7/49頁
文件大?。?/td> 567K
代理商： EDD5116AFTA-7B-E
EDD5108AFTA, EDD5116AFTA
Data Sheet E0699E20 (Ver. 2.0)
7
-6B
-7A
-7B
Parameter
Symbol
min.
max.
min.
max
min.
max.
Unit Notes
Address and control input pulse width tIPW
2.2
—
2.2
—
2.2
—
ns
7
Mode register set command cycle
time
tMRD
2
—
2
—
2
—
tCK
Active to Precharge command period tRAS
42
120000
45
120000
45
120000
ns
Active to Active/Auto refresh
command period
Auto refresh to Active/Auto refresh
command period
tRC
60
—
65
—
65
—
ns
tRFC
72
—
75
—
75
—
ns
Active to Read/Write delay
tRCD
18
—
20
—
20
—
ns
Precharge to active command period tRP
18
—
20
—
20
—
ns
Active to Autoprecharge delay
tRAP
tRCD min. —
tRCD min. —
tRCD min. —
ns
Active to active command period
tRRD
12
—
15
—
15
—
ns
Write recovery time
tWR
15
—
15
—
15
—
ns
Auto precharge write recovery and
precharge time
Internal write to Read command
delay
tDAL
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
—
(tWR/tCK)+
(tRP/tCK)
—
tCK 13
tWTR
1
—
1
—
1
—
tCK
Average periodic refresh interval
tREF
—
7.8
—
7.8
—
7.8
μs
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
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