參數(shù)資料
型號(hào): EDD51321CBH-7ETT-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits DDR SDRAM
中文描述: 16M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA90
封裝: ROHS COMPLIANT, FBGA-90
文件頁(yè)數(shù): 14/55頁(yè)
文件大小: 589K
代理商: EDD51321CBH-7ETT-E
EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
14
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0 and BA1 (See Bank Select Signal Table) and determines
the row address (Address Pins Table in “Pin Function”).
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0 and BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another
is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it
works. The both mode registers are set through the address pins in the mode register set cycle. For details, refer to
"Mode register and extended mode register set".
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