參數(shù)資料
型號(hào)： EDD51321CBH-7ETT-E
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 512M bits DDR SDRAM
中文描述： 16M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA90
封裝： ROHS COMPLIANT, FBGA-90
文件頁(yè)數(shù)： 17/55頁(yè)
文件大小： 589K
代理商： EDD51321CBH-7ETT-E
EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
17
Current state
Write with auto pre-
charge*
1
/CS
/RAS /CAS /WE
Address
Command
Operation
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
14
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL*
14
L
L
H
H
BA, RA
ACT
ILLEGAL*
11, 14
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11, 14
Remark: H: VIH. L: VIL.
×
: Don’t care.
Notes: 1. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued.
2. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued.
3. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued.
4. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued.
5. The DDR SDRAM is in "Active" state after "Activating" is completed.
6. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned
off.
7. The DDR SDRAM is in "READ with auto precharge" from READA command until burst data has been
output and DQ output circuits are turned off.
8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.
9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input.
10. The DDR SDRAM is in "Write with auto precharge" until tWR after the last data has been input.
11. This command may be issued for other banks, depending on the state of the banks.
12. All banks must be in "IDLE".
13. Before executing a write command to stop the preceding burst read operation, BST command must be
issued.
14. The DDR SDRAM supports the concurrent auto precharge feature, a read with auto precharge or a write
with auto precharge, can be followed by any command to the other banks, as long as that command does
not interrupt the read or write data transfer, and all other related limitations apply (e.g. contention between
READ data and WRITE data must be avoided.)
The minimum delay from a read or write command with auto precharge, to a command to a different bank,
is summarized below.
From command
interrupting command)
L
L
L
×
×
ILLEGAL
To command (different bank, non-
Minimum delay
(Concurrent AP supported)
Units
Read w/AP
Read or Read w/AP
BL/2
tCK
Write or Write w/AP
CL (rounded up)+ (BL/2)
tCK
Precharge or Activate
1
tCK
Write w/AP
Read or Read w/AP
1 + (BL/2) + tWTR
tCK
Write or Write w/AP
BL/2
tCK
Precharge or Activate
1
tCK
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