參數(shù)資料
型號： EDD51321CBH-7ETT-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits DDR SDRAM
中文描述： 16M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA90
封裝： ROHS COMPLIANT, FBGA-90
文件頁數(shù)： 7/55頁
文件大?。?/td> 589K
代理商： EDD51321CBH-7ETT-E
EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
7
-6C
-7E
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
7
Write command to first DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time
tDSS
0.2
—
0.2
—
tCK
DQS falling edge hold time from CK
tDSH
0.2
—
0.2
—
tCK
DQS input high pulse width
tDQSH
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
0.35
—
tCK
Address and control input setup time tIS
1.1
—
1.3
—
ns
3
Address and control input hold time
tIH
1.1
—
1.3
—
ns
3
Address and control input pulse width tIPW
2.7
—
3.0
—
ns
3
Mode register set command cycle
time
tMRD
2
—
2
—
tCK
Active to Precharge command period tRAS
42
120000
45
120000
ns
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period
tRC
66
—
75
—
ns
tRFC
108
—
108
—
ns
Active to Read/Write delay
tRCD
24
—
30
—
ns
Precharge to active command period tRP
24
—
22.5
—
ns
Column address to column address
delay
tCCD
1
—
1
—
tCK
Active to active command period
tRRD
12
—
15
—
ns
Write recovery time
tWR
15
—
15
—
ns
Autoprecharge write recovery and
precharge time
tDAL
tWR + tRP
—
tWR + tRP
—
ns
Self-Refresh Exit Period
tSREX
120
—
120
—
ns
Internal Write to Read command
delay
tWTR
2
—
1
—
tCK
Average periodic refresh interval
tREF
—
7.8
—
7.8
μs
Notes: 1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver
strength is assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VDDQ/2.
3. The timing reference level is VDDQ/2.
4. Output valid window is defined to be the period between two successive transition of data out signals.
The signal transition is defined to occur when the signal level crossing VDDQ/2.
5. tHZ is defined as DOUT transition delay from low-Z to high-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from high-Z to low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
8. tAC, tDQSCK, tHZ and tLZ are specified with 15pF bus loading conditio
n.
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