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參數(shù)資料
| 型號(hào)： | EDE1116ABSE-5C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 1G bits DDR2 SDRAM |
| 中文描述： | 64M X 16 DDR DRAM, 0.5 ns, PBGA92 |
| 封裝： | ROHS COMPLIANT, FBGA-92 |
| 文件頁(yè)數(shù)： | 17/82頁(yè) |
| 文件大?。?/td> | 618K |
| 代理商： | EDE1116ABSE-5C-E |
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EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Data Sheet E0852E50 (Ver. 5.0)
17
-5C
-4A
Frequency (Mbps)
533
400
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Active bank A to active bank B command
period
(EDE1104AB, EDE1108AB)
(EDE1116AB)
Four active window period
(EDE1104AB, EDE1108AB)
(EDE1116AB)
tRRD
7.5
7.5
ns
tRRD
10
10
ns
tFAW
37.5
37.5
ns
tFAW
50
50
ns
/CAS to /CAS command delay
tCCD
2
2
tCK
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
tWR
15
WR +
RU(tRP/tCK)
7.5
15
WR +
RU(tRP/tCK)
10
ns
tDAL
tCK
1, 9
tWTR
ns
Internal read to precharge command delay
tRTP
7.5
7.5
ns
Exit self-refresh to a non-read command
tXSNR
tRFC + 10
tRFC + 10
ns
Exit self-refresh to a read command
Exit precharge power-down to any non-read
command
Exit active power-down to read command
Exit active power-down to read command
(slow exit/low power mode)
CKE minimum pulse width (high and low
pulse width)
Output impedance test driver delay
tXSRD
200
200
tCK
tXP
2
2
tCK
tXARD
2
2
tCK
3
tXARDS
6
AL
6
AL
tCK
2, 3
tCKE
3
3
tCK
tOIT
0
12
0
12
ns
MRS command to ODT update delay
Auto-refresh to active/auto-refresh command
time
Average periodic refresh interval
(0
°
C
≤
TC
≤
+85
°
C)
(+85
°
C
<
TC
≤
+95
°
C)
Minimum time clocks remains ON after CKE
asynchronously drops low
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power-down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
t
MOD
0
12
0
12
ns
tRFC
127.5
127.5
ns
tREFI
7.8
7.8
μ
s
tREFI
tIS + tCK +
tIH
3.9
tIS + tCK +
tIH
3.9
μ
s
tDELAY
ns
DQS
/DQS
tDS
tDH
tDS
tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
CK
/CK
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE2104ABSE | 2G bits DDR2 SDRAM |
| EDE2104ABSE-5C-E | 2G bits DDR2 SDRAM |
| EDE2104ABSE-6E-E | 2G bits DDR2 SDRAM |
| EDE2104ABSE-8G-E | 2G bits DDR2 SDRAM |
| EDE2108ABSE | 2G bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE1116ABSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM |
| EDE1116ACBG | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM |
| EDE1116ACBG-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM |
| EDE1116ACBG-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM |
| EDE1116ACBG-8E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM |
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