參數(shù)資料
型號(hào)： EDE1116ABSE-5C-E
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 1G bits DDR2 SDRAM
中文描述： 64M X 16 DDR DRAM, 0.5 ns, PBGA92
封裝： ROHS COMPLIANT, FBGA-92
文件頁(yè)數(shù)： 23/82頁(yè)
文件大?。?/td> 618K
代理商： EDE1116ABSE-5C-E
EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Data Sheet E0852E50 (Ver. 5.0)
23
Input Slew Rate Derating
For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data
sheet tIS (base), tDS (base) and tIH (base), tDH (base) value to the
Δ
tIS,
Δ
tDS and
Δ
tIH,
Δ
tDH derating value
respectively.
Example: tDS (total setup time) = tDS (base) +
Δ
tDS.
Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF
(DC) and the first crossing of VIH (AC) min. Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the
slew rate between the last crossing of VREF (DC) and the first crossing of VIL (AC) max. If the actual signal is
always earlier than the nominal slew rate line between shaded ‘VREF (DC) to AC region’, use nominal slew rate for
derating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF (DC) to AC region’, the
slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value (see the figure
of Slew Rate Definition Tangent).
Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL (DC) max. and the first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH (DC) min. and the first crossing of VREF (DC). If the actual signal
is always later than the nominal slew rate line between shaded ‘DC level to VREF (DC) region’, use nominal slew
rate for derating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF (DC) region’,
the slew rate of a tangent line to the actual signal from the DC level to VREF (DC) level is used for derating value
(see the figure of Slew Rate Definition Tangent).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
VIH/IL (AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach VIH/IL (AC).
For slew rates in between the values listed in the tables below, the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[Derating Values of tDS/tDH with Differential DQS (DDR2-400, 533)]
DQS, /DQS differential slew rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH Unit
2.0
+125 +45 +125 +45 +125 +45
ps
1.5
+83 +21 +83 +21 +83 +21 +95 +33
ps
1.0
0
0
0
0
0
0
+12 +12 +24 +24
ps
0.9
11
14
11
14 +1
2
+13 +10 +25 +22
ps
0.8
25
31
13
19
1
7
11
+5
+23 +17
ps
0.7
31
42
19
30
7
18 +5
6
+17 +6
ps
0.6
43
59
31
47
19
35
7
23 +5
11 ps
0.5
74
89
62
77
50
65
38
53 ps
DQ
slew
rate
(V/ns)
0.4
127
140
115
128
103
116 ps
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDE1116ABSE-6E-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1G bits DDR2 SDRAM
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EDE1116ACBG-5C-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1G bits DDR2 SDRAM
EDE1116ACBG-6E-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1G bits DDR2 SDRAM
EDE1116ACBG-8E-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1G bits DDR2 SDRAM
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