參數(shù)資料
型號(hào)： EDE2108ABSE
廠商： Elpida Memory, Inc.
英文描述： 2G bits DDR2 SDRAM
中文描述： 第二代位DDR2 SDRAM內(nèi)存
文件頁(yè)數(shù)： 9/81頁(yè)
文件大?。?/td> 604K
代理商： EDE2108ABSE
EDE2104ABSE, EDE2108ABSE
Preliminary Data Sheet E1196E10 (Ver. 1.0)
9
max.
Parameter
Symbol
Grade
×
4
×
8
Unit
Test condition
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-Refresh Mode;
CK and /CK at 0V;
CKE
≤
0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
1
×
tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),
tFAW = tFAW (IDD), tRCD = 1
×
tCK (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Auto-refresh current
IDD5
-8G
-6E
-5C
TBD
TBD
TBD
TBD
TBD
TBD
mA
Self-refresh current
IDD6
TBD
TBD
mA
Operating current
(Bank interleaving)
IDD7
-8G
-6E
-5C
TBD
TBD
TBD
TBD
TBD
TBD
mA
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤
VIL (AC) (max.)
H is defined as VIN
≥
VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
相關(guān)PDF資料
PDF描述
EDE2108ABSE-5C-E 2G bits DDR2 SDRAM
EDE2108ABSE-6E-E 2G bits DDR2 SDRAM
EDE2108ABSE-8G-E 2G bits DDR2 SDRAM
EDE2508ABSE 256M bits DDR2 SDRAM
EDE2508ABSE-5C-E 256M bits DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDE2108ABSE-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM
EDE2108ABSE-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM
EDE2108ABSE-8G-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM
EDE2108AEBG 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:Lead-free (RoHS compliant) and Halogen-free
EDE2108AEBG-8E-F 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:Lead-free (RoHS compliant) and Halogen-free
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