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參數(shù)資料
| 型號： | EDE2508ABSE-GE-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 256M bits DDR2 SDRAM for HYPER DIMM |
| 中文描述： | 32M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 39/66頁 |
| 文件大小： | 708K |
| 代理商： | EDE2508ABSE-GE-E |
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EDE2508ABSE, EDE2516ABSE
Preliminary Data Sheet E0573E30 (Ver. 3.0)
39
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory
locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst
length. DDR2 SDRAM supports 4 bits burst and 8bits burst modes only. For 8 bits burst mode, full interleave
address ordering is supported, however, sequential address ordering is nibble based for ease of implementation.
The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS,
which is similar to the DDR-I SDRAM operation. Seamless burst read or write operations are supported.
Unlike DDR-I devices, interruption of a burst read or writes operation is limited to ready by Read or Write by Write at
the boundary of Burst 4. Therefore the burst stop command is not supported on DDR2 SDRAM devices.
[Burst Length and Sequence]
Burst length
Starting address (A2, A1, A0) Sequential addressing (decimal)
Interleave addressing (decimal)
000
0, 1, 2, 3
0, 1, 2, 3
001
1, 2, 3, 0
1, 0, 3, 2
010
2, 3, 0, 1
2, 3, 0, 1
4
011
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
8
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Note: Page length is a function of I/O organization and column addressing
8M bits
×
8 organization (CA0 to CA9); Page Length = 1024 bits
4M bits
×
16 organization (CA0 to CA8); Page Length = 512 bits
相關PDF資料 |
PDF描述 |
|---|---|
| EDE2516ABSE | 256M bits DDR2 SDRAM |
| EDE2516ABSE-GE-E | 256M bits DDR2 SDRAM for HYPER DIMM |
| EDE5104ABSE | 512M bits DDR2 SDRAM |
| EDE5104AGSE | 512M bits DDR2 SDRAM |
| EDE5108AGSE | Circular Connector; No. of Contacts:6; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:17-6 RoHS Compliant: No |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EDE2508ACSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM |
| EDE2508ACSE-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM |
| EDE2508ACSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM |
| EDE2508ACSE-8E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM |
| EDE2508AEBG | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM |
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