- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3800 > EFM32TG232F32 (Energy Micro)IC MCU 32BIT 32KB FLASH 64LQFP PDF資料下載
參數(shù)資料
| 型號： | EFM32TG232F32 |
| 廠商： | Energy Micro |
| 文件頁數(shù)： | 29/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 32KB FLASH 64LQFP |
| 特色產(chǎn)品： | EFM32 Tiny Gecko |
| 標準包裝： | 1 |
| 系列： | Tiny Gecko |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 32MHz |
| 連通性： | I²C，IrDA，智能卡，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，I²S，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 53 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.8 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 1x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 標準包裝 |
| 其它名稱： | 914-1030-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
124
www.energymicro.com
Glossary
This glossary describes some of the terms used in technical documents from ARM.
Abort
A mechanism that indicates to a processor that the value associated with a
memory access is invalid. An abort can be caused by the external or internal
memory system as a result of attempting to access invalid instruction or data
memory.
Aligned
A data item stored at an address that is divisible by the number of bytes that
defines the data size is said to be aligned. Aligned words and halfwords have
addresses that are divisible by four and two respectively. The terms word-
aligned and halfword-aligned therefore stipulate addresses that are divisible
by four and two respectively.
Banked register
A register that has multiple physical copies, where the state of the processor
determines which copy is used. The Stack Pointer, SP (R13) is a banked
register.
Base register
In instruction descriptions, a register specified by a load or store instruction
that is used to hold the base value for the instruction’s address calculation.
Depending on the instruction and its addressing mode, an offset can be
added to or subtracted from the base register value to form the address that
is sent to memory.
See Also Index register.
Big-endian (BE)
Byte ordering scheme in which bytes of decreasing significance in a data
word are stored at increasing addresses in memory.
See Also Byte-invariant, Endianness, Little-endian.
Big-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the most significant byte
or halfword within the word at that address
a byte at a halfword-aligned address is the most significant byte within the
halfword at that address.
See Also Little-endian memory.
Breakpoint
A breakpoint is a mechanism provided by debuggers to identify an instruction
at which program execution is to be halted. Breakpoints are inserted by the
programmer to enable inspection of register contents, memory locations,
variable values at fixed points in the program execution to test that the
program is operating correctly. Breakpoints are removed after the program
is successfully tested.
Byte-invariant
In a byte-invariant system, the address of each byte of memory remains
unchanged when switching between little-endian and big-endian operation.
When a data item larger than a byte is loaded from or stored to memory,
the bytes making up that data item are arranged into the correct order
depending on the endianness of the memory access. An ARM byte-
invariant implementation also supports unaligned halfword and word memory
accesses. It expects multi-word accesses to be word-aligned.
Cache
A block of on-chip or off-chip fast access memory locations, situated between
the processor and main memory, used for storing and retrieving copies of
often used instructions, data, or instructions and data. This is done to greatly
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P80C32X2FA,512 | IC 80C51 MCU 256 ROMLESS 44PLCC |
| LPC1224FBD64/101,1 | MCU 32BIT 32K FLASH 4K 64-LQFP |
| R5F72165GDFA#V0 | MCU 512K FLASH 64K 176-LQFP |
| R5F72165ADFA#V0 | MCU 512K FLASH 64K 176-LQFP |
| EFM32TG222F32 | IC MCU 32BIT 32KB FLASH 48LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EFM32TG232F32-QFP64 | 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 64TQFP |
| EFM32TG232F32-QFP64T | 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, TINY GECKO - Trays |
| EFM32TG232F32-QFP64-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 64TQFP |
| EFM32TG232F32-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 64TQFP |
| EFM32TG232F8 | 功能描述:ARM微控制器 - MCU 8kb flash 2kb RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。