參數(shù)資料
型號: EFM32TG232F32
廠商: Energy Micro
文件頁數(shù): 83/136頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 32KB FLASH 64LQFP
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1030-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
50
www.energymicro.com
LDRSB
R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
; sum of R5 and two times R1, sign extended it
; to a word value and put it in R0
STR
R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
; and four times R2
3.4.4 LDR and STR, unprivileged
Load and Store with unprivileged access.
3.4.4.1 Syntax
op{type}T{cond} Rt, [Rn {, #offset}]
; immediate offset
where:
op
is one of:
LDR
Load Register.
STR
Store Register.
type
is one of:
B
unsigned byte, zero extend to 32 bits on loads.
SB
signed byte, sign extend to 32 bits (LDR only).
H
unsigned halfword, zero extend to 32 bits on loads.
SH
signed halfword, sign extend to 32 bits (LDR only).
#
omit, for word.
cond
is an optional condition code, see Section 3.3.7 (p. 43) .
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
offset
is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn.
3.4.4.2 Operation
These load and store instructions perform the same function as the memory access instructions with
immediate offset, see Section 3.4.2 (p. 46) . The difference is that these instructions have only
unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as normal
memory access instructions with immediate offset.
3.4.4.3 Restrictions
In these instructions:
Rn must not be PC
Rt must not be SP and must not be PC.
3.4.4.4 Condition flags
These instructions do not change the flags.
3.4.4.5 Examples
STRBTEQ
R4, [R7]
; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
LDRHT
R2, [R2, #8]
; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
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