參數(shù)資料
型號: EM78P870
廠商: ELAN Microelctronics Corp .
元件分類: 8位微控制器
英文描述: 8 BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁數(shù): 17/48頁
文件大小: 313K
代理商: EM78P870
EM78P870
8-bit OTP Micro-controller
_________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
14
8/19/2004 (V1.5)
basis of both the clock rate and the selected edge.
Bit 0
SPI module
SCK
Bit7
Salve Device
SPIR register
SDI
SPIW register
SPIS Reg
SDO
SDO
SCK
SDI
Master Device
R5 page1
Fig.6 Single SPI Master / Salve Communication
Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits
SBRS2(Bit 2)
SBRS1(Bit 1)
SBRS0(Bit 0)
Mode
Baud rate
0
0
0
0
0
1
Master
Master
Fsco
Fsco/2
0
1
0
Master
Fsco/4
0
1
1
Master
Fsco/8
1
0
0
Master
Fsco/16
1
0
1
Master
Fsco/32
1
1
0
Slave
1
1
1
x
x
<Note> Fsco = CPU instruction clock
For example :
If PLL enable and RA PAGE0 (Bit5,Bit4)=(1,1), instruction clock is 3.58MHz/2
Fsco=3.5862MHz/2
If PLL enable and RA PAGE0 (Bit5,Bit4)=(0,0), instruction clock is 0.895MHz/2
Fsco=0.895MHz/2
If PLL disable, instruction clock is 32.768kHz/2
Fsco=32.768kHz/2.
Bit 3 (SCES) : SPI clock edge selection bit
1
Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level.
0
Data shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level.
Bit 4 (SE) : SPI shift enable bit
1
Start to shift, and keep on 1 while the current byte is still being transmitted.
0
Reset as soon as the shifting is complete, and the next byte is ready to shift.
<Note> This bit has to be reset in software.
Bit 5 (SRO) : SPI read overflow bit
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