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參數(shù)資料
| 型號： | EM78P870 |
| 廠商： | ELAN Microelctronics Corp . |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 42/48頁 |
| 文件大?。?/td> | 313K |
| 代理商： | EM78P870 |
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EM78P870
8-bit OTP Micro-controller
_________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
39
8/19/2004 (V1.5)
A
Address
R register
Page0
R register
Page1
IOC
Register
Page0
11100000
11111111
11111111
11111111
11111111
00000000
11111111
11111111
00000000
00000000
00000000
IOC
Register
page1
00000000
-
11111111
11111111
-
00000000
00000000
00000000
00000000
00000000
-
IOC
Register
4
5
6
7
8
9
A
B
C
D
E
F
000xxxxx
00xxxxxx
xxx00000
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
00000110
xxxxxxxx
xxxxxxxx
00000000
10000000
00000000
00000000
xxxxxxxx
xxxxxxxx
Xxxxxxxx
Xxxxxxxx
x0000000
Xxxxxxxx
Xxxxxxxx
Xxxxxxxx
Xxxxxxxx
000xxxxx
-
00000000
00000000
VII.7 wake-up
The controller provided sleep mode for power saving.
SLEEP mode , RA(7)=0 + "SLEP" instruction .
The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or
PLL control (which has enable register), user has to turn it off by software.
Wake-up from SLEEP mode
(1) WDT time out
(2) external interrupt
(3) /RESET pull low
All these cases will reset controller , and run the program at address zero. The status just like the power on reset.
Be sure to enable circuit at case (1) or (2).
VII.8 Interrupt
RF is the interrupt status register which records the interrupt request in flag bits. IOCF is the interrupt mask
register. TCC timer, Counter1 and Counter2 are internal interrupt source. P70 ~ P77(INT0 ~ INT1) are external
interrupt input which interrupt sources are come from the external. If the interrupts are happened by these
interrupt sources, then RF register will generate '1' flag to corresponding register if you enable IOCF register.
Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts
(when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt
service routine the source of the interrupt can be determined by polling the flag bits in the RF register. The
interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts
to avoid recursive interrupts.
CAS pin goes to low.
VII.10 Instruction Set
Instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register.
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