參數(shù)資料
型號： Embedded Pentium 100
廠商： Intel Corp.
英文描述： 32 Bit Embedded Pentium Processor(32位嵌入式奔騰處理器)
中文描述： 32位嵌入式奔騰處理器（32位嵌入式奔騰處理器）
文件頁數(shù)： 19/42頁
文件大?。?/td> 882K
代理商： EMBEDDED PENTIUM 100
Embedded Pentium
Processor
Datasheet
19
HLDA
O
The
bus hold acknowledge
pin goes active in response to a hold request driven to
the processor on the HOLD pin. It indicates that the processor has floated most of
the output pins and relinquished the bus to another local bus master. When leaving
bus hold, HLDA is driven inactive and the processor resumes driving the bus. When
the processor has a bus cycle pending, it is driven in the same clock in which HLDA
is deasserted.
HOLD
I
In response to the
bus hold request
, the processor floats most of its output and
input/output pins and asserts HLDA after completing all outstanding bus cycles. The
processor maintains its bus in this state until HOLD is deasserted. HOLD is not
recognized during LOCK cycles. The processor recognizes HOLD during reset.
IERR#
O
The
internal error
pin is used to indicate two types of errors, internal parity errors
and functional redundancy errors. When a parity error occurs on a read from an
internal array, the processor asserts the IERR# pin for one clock and then shuts
down. When the processor is configured as a checker and a mismatch occurs
between the value sampled on the pins and the corresponding value computed
internally, the processor asserts IERR# two clocks after the mismatched value is
returned.
LOCK#
O
The
bus lock
pin indicates that the current bus cycle is locked. The processor does
not allow a bus hold when LOCK# is asserted (but AHOLD and BOFF# are allowed).
LOCK# goes active in the first clock of the first locked bus cycle and goes inactive
after the BRDY# is returned for the last locked bus cycle. LOCK# is guaranteed to be
deasserted for at least one clock between back-to-back locked cycles.
M/IO#
O
The
memory/input-output
is one of the primary bus cycle definition pins. It is driven
valid in the same clock in which the ADS# signal is asserted. M/IO# distinguishes
between memory and I/O cycles.
NA#
I
An active
next address
input indicates that the external memory system is ready to
accept a new bus cycle although all data transfers for the current cycle have not yet
completed. The processor issues ADS# for a pending cycle two clocks after NA# is
asserted. The processor supports up to two outstanding bus cycles.
NMI/LINT1
I
The
non-maskable interrupt
request signal indicates that an external non-
maskable interrupt has been generated.
When the local APIC is enabled, this pin becomes LINT1.
PBGNT#
I/O
When two Pentium processors are configured in dual processing mode,
Private bus
grant
is the grant line that is used to perform private bus arbitration. PBGNT# should
be left unconnected if only one Pentium processor exists in a system.
PBREQ#
I/O
When two Pentium processors are configured in dual processing mode,
Private bus
request
is the request line that is used to perform private bus arbitration. PBREQ#
should be left unconnected if only one Pentium processor exists in a system.
PCD
O
The
page cacheability disable
pin reflects the state of the PCD bit in CR3, the
Page Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an
external cacheability indication on a page-by-page basis.
PCHK#
O
The
data
parity check
output indicates the result of a parity check on a data read. It
is driven with parity status two clocks after BRDY# is returned. PCHK# remains low
one clock for each clock in which a parity error was detected. Parity is checked only
for the bytes on which valid data is returned.
When two Pentium processors are operating in dual processing mode, PCHK# may
be driven two or three clocks after BRDY# is returned.
PEN#
I
The
parity enable
input (along with CR4.MCE) determines whether a machine
check exception is taken as a result of a data parity error on a read cycle. When this
pin is sampled active in the clock during which a data parity error is detected, the
processor latches the address and control signals of the cycle with the parity error in
the machine check registers. When PEN# is active and the machine check enable
bit in CR4 is set to “1”, the processor vectors to the machine check exception before
the beginning of the next instruction.
The pins are classified as Input or Output based on their function in Master Mode. See the Pentium
Processor
Family Developer’s Manual
(order number 273204) for more information.
Table 4. Pin Quick Reference (Sheet 4 of 5)
Symbol
Type
Name and Function
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