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參數(shù)資料
| 型號： | Embedded Pentium 100 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor(32位嵌入式奔騰處理器) |
| 中文描述： | 32位嵌入式奔騰處理器（32位嵌入式奔騰處理器） |
| 文件頁數(shù)： | 37/42頁 |
| 文件大?。?/td> | 882K |
| 代理商： | EMBEDDED PENTIUM 100 |
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Embedded Pentium
Processor
Datasheet
37
Table 21. Notes for Tables 19 and 20
1. Not 100% tested. Guaranteed by design/characterization.
2. Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to boundary scan operations.
3. APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch-free outputs. Glitch-free signals
monotonically transition without false transitions.
4. Referenced to TCK rising edge.
5. Referenced to TCK falling edge.
6. 1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz.
7. During probe mode operation, do not use the boundary scan timings (t
).
8. FRCMC# should be tied to V
CC
(high) to ensure proper operation of the Pentium processor as a primary
processor.
9. Setup time is required to guarantee recognition on a specific clock. The Pentium processor must meet this
specification for dual processor operation for the FLUSH# and RESET signals.
10.Hold time is required to guarantee recognition on a specific clock. The Pentium processor must meet this
specification for dual processor operation for the FLUSH# and RESET signals.
11.To guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a
minimum of two clocks before being returned active and must meet the minimum pulse width.
12.This input may be driven asynchronously. However, when operating two processors in dual processing
mode, FLUSH# and RESET must be asserted synchronously to both processors.
13.When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, and SMI# must be deasserted (inactive)
for a minimum of two clocks before being returned active.
14.Timings are valid only when dual processor is present.
15.Maximum time DPEN# is valid from rising edge of RESET.
16.Minimum time DPEN# is valid after falling edge of RESET.
17.
The D/C#, M/IO#, W/R#, CACHE#, and A31–A5 signals are sampled only on the CLK during which ADS#
is active.
18.BF and CPUTYP should be strapped to V
or V
.
19.RESET is synchronous in dual processing mode and functional redundancy checking mode. All signals
that have a setup or hold time with respect to a falling or rising edge of RESET in UP mode should be
measured with respect to the first processor clock edge in which RESET is sampled either active or
inactive in dual processing and functional redundancy checking modes.
20.The PHIT# and PHITM# signals operate at the core frequency.
21.These signals are measured on the rising edge of adjacent CLKs at 1.5 V. To ensure a 1:1 relationship
between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum
should not have any power spectrum peaking between 500 KHz and 1/3 of the CLK operating frequency.
The amount of jitter present must be accounted for as a component of CLK skew between devices.
22.In dual processing mode, timing t
is replaced by t
. Timing t
is required for external snooping (e.g.,
address setup to the CLK in which EADS# is sampled active) in both uniprocessor and dual processor
modes.
23.BRDYC# and BUSCHK# are used as reset configuration signals to select buffer size.
24.This assumes an external pullup resistor to V
and a lumped capacitive load. The pullup resistor must be
between 300 Ohms and 1 KOhms, the capacitance must be between 20 pF and 120 pF, and the RC
product must be between 3 ns and 36 ns. V
for PICD1–PICD0 is 0.55 V.
25.This is a flight time specification that includes both flight time and clock skew. The flight time is the time
from when the unloaded driver crosses 1.5 V (50% of min. V
CC
), to when the receiver crosses the 1.5 V
level (50% of min. V
). See Figure 13.
26.This is for the lock-step operation of the component only. This guarantees that APIC interrupts will be
recognized on specific clocks to support two processors running in a lock step fashion, including FRC
mode. FRC on the APIC pins is not supported but mismatches on these pins will result in a mismatch on
other pins of the CPU.
27.The CLK to PICCLK ratio for lock-step operation must be an integer and the ratio (CLK/PICCLK) cannot be
smaller than 4:1.
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