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參數(shù)資料
| 型號(hào)： | Embedded Pentium 100 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor(32位嵌入式奔騰處理器) |
| 中文描述： | 32位嵌入式奔騰處理器（32位嵌入式奔騰處理器） |
| 文件頁數(shù)： | 32/42頁 |
| 文件大小： | 882K |
| 代理商： | EMBEDDED PENTIUM 100 |
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Embedded Pentium
Processor
32
Datasheet
3.5.3
Decoupling Recommendations
Liberal decoupling capacitance should be placed near the processor. Transient power surges can
occur when the processor is driving its address and data buses at high frequencies. This is most
common when driving large capacitive loads.
Low inductance capacitors and interconnects are recommended for best high frequency electrical
performance. Inductance can be reduced by minimizing the length of the circuit board traces
between the processor and the decoupling capacitors.
These capacitors should be evenly distributed around each component on the 3.3 V plane.
Capacitor values should be chosen to ensure that they eliminate both low and high frequency noise
components.
For the Pentium processor, the power consumption can transition from a low power level to a much
higher level (or high-to-low power) very rapidly. A typical example is when entering or exiting the
Stop Grant state. Other examples are when executing a HALT instruction (causing the processor to
enter the Auto HALT Powerdown state) or when transitioning from HALT to the Normal state. All
these examples may cause abrupt changes in the power being consumed by the processor. Note that
the Auto HALT Powerdown feature is always enabled even when other power management
features are not implemented.
Bulk storage capacitors with a low ESR (Effective Series Resistance) in the 10 to 100 μF range are
required to maintain a regulated supply voltage during the interval between the time the current
load changes and the point at which the regulated power supply output reacts to the change in load.
In order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel.
These capacitors should be placed near the processor (on the 3.3 V plane) to ensure that the supply
voltage stays within specified limits during changes in the supply current during operation.
3.5.4
Connection Specifications
All NC and INC pins must remain unconnected. For reliable operation, always connect unused
inputs to an appropriate signal level. Unused active low inputs should be connected to V
CC
. Unused
active high inputs should be connected to ground.
3.5.5
AC Timing Tables
The AC specifications given in Table 19 and Table 20 consist of output delays, input setup
requirements and input hold requirements for a 66-MHz external bus. All AC specifications (with
the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the
CLK input.
All timings are referenced to 1.5 V for both “0” and “1” logic levels unless otherwise specified.
Within the sampling window, a synchronous input must be stable for correct processor operation.
Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer models to
account for signal flight time delays.
The following applies to all standard TTL signals used with the Pentium processor family:
TTL input test waveforms are assumed to be 0 to 3 V transitions with 1 V/ns rise and fall
times.
0.3 V/ns
≤
input rise/fall time
≤
5 V/ns.
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